Time delay circuit

Claim 1

A TIME DELAY CIRCUIT COMPRISING A RESISTOR, A CAPACITOR AND A FIRST TRANSISTOR COUPLED TOGETHER BETWEEN A VOLTAGE SUPPLY AND A SWITCH, SAID TRANSISTOR HAVING A BASE, A COLLECTOR AND AN EMITTER TERMINAL, MEANS CONNECTING SAID BASE TERMINAL TO SAID SWITCH, MEANS CONNECTING SAID COLLECTOR TERMINAL AND SAID BASE TERMINAL TO SEPARATE TERMINALS OF SAID CAPACITOR, MEANS CONNECTING SAID RESISTOR BETWEEN SAID COLLECTOR TERMINAL AND SAID VOLTAGE SUPPLY, A SECOND TRANSISTOR HAVING A BASE TERMINAL AND A COLLECTOR TERMINAL, MEANS CONNECTING THE COLLECTOR TERMINAL OF SAID FIRST TRANSISTOR TO THE BASE TERMINAL OF SAID SECOND TRANSISTOR, AND A RELAY COIL CONNECTED BETWEEN THE EMITTER TERMINAL OF SAID SECOND TRANSISTOR AND THE SWITCH, WHEREBY THE FIRST TRANSISTOR FUNCTIONS TO MULTIPLY THE DELAY TIME INHERENT IN THE COMBINATION OF THE RESISTOR AND THE CAPACITOR BY A MAGNITUDE PROPORTIONAL TO THE CURRENT GAIN OF THE FIRST TRANSISTOR, AND THE SECOND TRANSISTOR FUNCTIONS TO ISOLATE A SIGNAL APPLIED TO ITS INPUT TERMINAL FROM THE SIGNAL APPEARING ON ITS OUTPUT TERMINAL.