Electronic testing equipment

Claim 1

A DISTORTION LEVEL MONITOR HAVING AN INPUT TERMINAL, A GROUND TERMINAL, A FIRST CAPACITOR COUPLED TO THE INPUT TERMINAL, A FIRST RECTIFIER COUPLED TO THE FIRST CAPACITOR, THE PARALLEL COMBINATION OF A FIRST RESISTOR AND A SECOND CAPACITOR COUPLED BETWEEN THE FIRST RECTIFIER AND THE GROUND TERMINAL, A CENTER SCALE VOLTMETER HAVING TWO INPUT TERMINALS, ONE OF SAID INPUT TERMINALS BEING COUPLED TO THE FIRST RECTIFIER, A SECOND RESISTOR COUPLED TO THE INPUT TERMINAL, THE PARALLEL COMBINATION OF A THIRD CAPACITOR AND FIRST INDUCTOR COUPLED BETWEEN THE INPUT TERMINAL AND GROUND, A THIRD RESISTOR COUPLED TO THE SECOND RESISTOR, THE PARALLEL COMBINATION OF A SECOND INDUCTOR AND A FOURTH CAPACITOR COUPLED BETWEEN THE THIRD RESISTOR AND GROUND, A FIRST TRANSISTOR HAVING EMITTER, BASE, AND COLLECTOR, THE BASE OF THE FIRST TRANSISTOR BEING COUPLED TO THE THIRD RESISTOR AND BEING COUPLED THROUGH A FOURTH RESISTOR TO GROUND, THE EMITTER OF THE FIRST TRANSISTOR BEING COUPLED TO A FIRST VARIABLE RESISTOR, A WIPER ON THE FIRST VARIABLE RESISTOR BEING COUPLED THROUGH A FIFTH CAPACITOR TO GROUND, A SECOND TRANSISTOR HAVING EMITTER, BASE, AND COLLECTOR, THE BASE OF THE SECOND TRANSISTOR BEING COUPLED TO THE COLLECTOR OF THE FIRST TRANSISTOR, A THIRD TRANSISTOR HAVING EMITTER, BASE, AND COLLECTOR, THE BASE OF THE THIRD TRANSISTOR BEING COUPLED TO THE EMITTER OF THE SECOND TRANSISTOR, THE EMITTER OF THE THIRD TRANSISTOR BEING COUPLED THROUGH THE PARALLEL COMBINATION OF A FIFTH RESISTOR AND A SIXTH CAPACITOR TO GROUND, A FEEDBACK NETWORK BETWEEN THE COLLECTOR OF THE THIRD TRANSISTOR AND THE EMITTER OF THE FIRST TRANSISTOR, SAID FEEDBACK NETWORK COMPRISING THE PARALLEL COMBINATION OF A SEVENTH CAPACITOR, A SIXTH RESISTOR, AND A SEVENTH RESISTOR AND AN EIGHTH CAPACITOR IN SERIES, AN EIGHTH RESISTOR COUPLED TO THE COLLECTOR OF THE THIRD TRANSISTOR, THE PARALLEL COMBINATION OF A THIRD INDUCTOR AND A NINTH CAPACITOR COUPLED BETWEEN THE EIGHTH RESISTOR AND GROUND, A NINTH RESISTOR COUPLED TO THE EIGHTH RESISTOR, THE PARALLEL COMBINATION OF A FOURTH INDUCTOR AND A TENTH CAPACITOR COUPLED BETWEEN THE NINTH RESISTOR AND GROUND, A FOURTH TRANSISTOR HAVING AN EMITTER, BASE, AND COLLECTOR, THE BASE OF THE FOURTH TRANSISTOR BEING COUPLED TO THE NINTH RESISTOR AND COUPLED THROUGH A TENTH RESISTOR TO GROUND, THE EMITTER OF THE FOURTH TRANSISTOR BEING COUPLED TO A SECOND VARIABLE RESISTOR, A WIPER OF THE SECOND VARIABLE RESISTOR BEING COUPLED THROUGH AN ELEVENTH CAPACITOR TO GROUND, A FIFTH TRANSISTOR HAVING EMITTER, BASE, AND COLLECTOR, THE BASE OF THE FIFTH TRANSISTOR BEING COUPLED TO THE COLLECTOR OF THE FOURTH TRANSISTOR, A SIXTH TRANSISTOR HAVING EMITTER, BASE, AND COLLECTOR, THE BASE OF THE SIXTH TRANSISTOR BEING COUPLED TO THE EMITTER OF THE FIFTH TRANSISTOR, THE EMITTER OF THE SIXTH TRANSISTOR BEING COUPLED THROUGH THE PARALLEL COMBINATION OF AN ELEVENTH RESISTOR AND A TWELFTH CAPACITOR TO GROUND, A FEEDBACK CIRCUIT COUPLED BETWEEN THE COLLECTOR OF THE SIXTH TRANSISTOR AND THE EMITTER OF THE FOURTH TRANSISTOR, SAID FEEDBACK CIRCUIT COMPRISING THE PARALLEL COMBINATION OF A THIRTEENTH CAPACITOR, AN EIGHTEENTH RESISTOR, AND A FOURTEENTH CAPACITOR AND A NINETEENTH RESISTOR IN SERIES, A FIFTEENTH CAPACITOR COUPLED TO THE COLLECTOR OF THE SIXTH TRANSISTOR, A SEVENTH TRANSISTOR HAVING EMITTER, BASE, AND COLLECTOR, THE BASE OF THE SEVENTH TRANSISTOR BEING COUPLED DIRECTLY TO THE FIFTEENTH CAPACITOR, THE EMITTER OF THE SEVENTH TRANSISTOR BEING COUPLED AND THROUGH A SIXTEENTH CAPACITOR TO GROUND, AN EIGHTH TRANSISTOR HAVING EMITTER, BASE, AND COLLECTOR, THE BASE OF THE EIGHTH TRANSISTOR BEING COUPLED TO THE COLLECTOR OF THE SEVENTH TRANSISTOR, A NINTH TRANSISTOR HAVING EMITTER, BASE, AND COLLECTOR, THE BASE OF THE NINTH TRANSISTOR BEING COUPLED THROUGH A SEVENTEENTH CAPACITOR TO THE BASE OF THE EIGHTH TRANSISTOR, THE COLLECTOR OF THE NINTH TRANSISTOR BEING COUPLED THROUGH A FOURTEENTH RESISTOR TO THE COLLECTOR OF THE