US3360713A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power control circuits using bi-directional controllable semiconductor switching devices
Assignee: General Electric Co
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Filing: 1964-02-07
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Granted: 1967-12-26
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Expires: 1984-02-07
Abstract
No abstract record available.
Inventors
- 👤 Howell Edward Keith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:38
CPC Classifications
H; H05; H05B; H05B41/00; H05B41/14; H05B41/36; H05B41/38; H05B41/39; H05B41/392; H05B41/3921; H05B41/3924; G; G05; G05D; G05D23/00; G05D23/19; G05D23/1906; G05D23/20; G05D23/24; G05F; G05F1/00; G05F1/10; G05F1/12; G05F1/40; G05F1/44; G05F1/45; G05F1/455; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/72; H03K17/722; H03K17/723; H03K17/725; H10; H10D; H10D18/00; H10D18/80
Claims Analysis
Total Claims: 1
Claim 1
Independent Claim
247 words
IN COMBINATION, A BI-DIRECTIONAL CURRENT CONDUCTING SEMICONDUCTOR DEVICE NORMALLY EXHIBITING A HIGH IMPEDANCE CHARACTERISTIC BETWEEN TWO MAIN CURRENT CARRYING TERMINALS THEREOF AND EXHIBITING A LOW IMPEDANCE CHARACTERISTIC IN RESPONSE TO THE APPLICATION OF A CONTROL SIGNAL HAVING AT LEAST A PREDETERMINED AMPLITUDE TO A THIRD AND GATING TERMINAL THEREOF, THE MINIMUM VALUE OF SAID SIGNAL NECESSARY TO CAUSE LOW IMPEDANCE BEING THE SAME FOR BOTH DIRECTIONS OF CURRENT BETWEEN SAID TWO TERMINALS, MEANS SERIALLY CONNECTING SAID TWO MAIN TERMINALS IN A CURRENT CARRYING PATH TO A LOAD AND AN ALTERNATING CURRENT SOURCE, AND MEANS FOR PRODUCING FIRST AND SECOND RECTIFIER PORTIONS OF SAID SOURCE OUTPUT, A UNIJUNCTION TRANSISTOR RELAXATION OSCILLATOR INCLUDING A UNIJUNCTION TRANSISTOR HAVING A PAIR OF BASE ELECTRODES AND AN EMITTER ELECTRODE, AN ADJUSTABLE TIME CONSTANT CIRCUIT ASSOCIATED WITH SAID EMITTER ELECTRODE, MEANS FOR APPLYING SAID FIRST RECTIFIED PORTION ACROSS THE BASE TO BASE PATH OF SAID TRANSISTOR AND TO SAID TIME CONSTANT CIRCUIT TO PROVIDE SIGNALS OCCURRING IN SYNCHRONISM WITH AND IN VARYING PHASE RELATIONSHIP WITH HALF CYCLES OF THE SOURCE OUTPUT, A GATE CONTROLLED RECTIFIER, HAVING AN ANODE, CATHODE AND GATE ELECTRODE, MEANS FOR APPLYING SAID SECOND RECTIFIED PORTION ACROSS THE ANODE TO CATHODE OF SAID GATE CONTROLLED RECTIFIER, MEANS FOR APPLYING SAID SIGNALS TO SAID GATE ELECTRODE TO PRODUCE SAID CONTROL PULSES, AND MEANS FOR APPLYING SAID CONTROL PULSES BETWEEN SAID THRID TERMINAL AND THE SAME ONE OF SAID MAIN TERMINALS FOR BOTH DIRECTIONS OF CURRENT FLOW BETWEEN SAID TWO MAIN TERMINALS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1970-12-25 | 1971-06-26 | 1971-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1974-12-25 | 1975-06-26 | 1975-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1978-12-25 | 1979-06-26 | 1979-12-26 | $7700.00 | Window Closed / Lapsed |