Solid state binary adder

Claim 1

A BINARY ADDER COMPRISING: (A) A VOLTAGE SOURCE; (B) A FIRST INPUT SECTION INCLUDING A FIRST PLURALITY OF SERIES CONNECTED TRANSISTORS CONNECTED ACROSS SAID VOLTAGE SOURCE; (C) A SECOND INPUT SECTION INCLUDING A SECOND PLURALITY OF SERIES CONNECTED TRANSISTORS CONNECTED ACROSS SAID VOLTAGE SOURCE; (D) A THIRD INPUT SECTION INCLUDING A THIRD PLURALITY OF SERIES CONNECTED TRANSISTORS CONNECTED ACROSS SAID VOLTAGE SOURCE; (E) A PLURALITY OF BINARY INPUT MEANS CONNECTED RESPECTIVELY TO EACH OF SAID TRANSISTORS; (F) BIASING MEANS COUPLED TO EACH OF SAID TRANSISTORS WHEREBY A BINARY "ONE" APPLIED TO ONE OF SAID TRANSISTORS WILL INITIATE CONDUCTION THEREOF; (G) A FIRST OUTPUT TRANSISTOR CONNECTED IN SERIES WITH AT LEAST ONE OF SAID TRANSISTORS OF EACH OF SAID INPUT SECTIONS; (H) SAID FIRST OUTPUT TRANSISTOR HAVING ITS BASE CONNECTED IN SERIES WITH AT LEAST TWO SERIES CONNECTED TRANSISTORS IN EACH OF SAID INPUT SECTIONS; (I) A SECOND OUTPUT TRANSISTOR CONNECTED IN PARALLEL WITH SAID FIRST OUTPUT TRANSISTOR THE STATE OF WHICH CONTROLS THE CARRY OUTPUT; (J) A THIRD OUTPUT TRANSISTOR THE STATE OF WHICH CONTROLS THE SUM OUTPUT; (K) A FOURTH OUTPUT TRANSISTOR CONNECTED IN SERIES WITH SAID THIRD OUTPUT TRANSISTOR; (L) SAID FOURTH OUTPUT TRANSISTOR BEING CONTROLLED BY SAID FIRST OUTPUT TRANSISTOR, WHEREBY WHEN SAID FIRST OUTPUT TRANSISTOR IS IN ONE STATE, SAID FOURTH OUTPUT TRANSISTOR IS IN THE OPPOSITE STATE; (M) SAID SERIES CONNECTED THIRD AND FOURTH TRANSISTORS CONNECTED ACROSS SAID VOLTAGE SOURCE; AND (N) SAID THIRD OUTPUT TRANSISTOR HAVING ITS BASE CONNECTED IN SERIES WITH SAID FIRST INPUT SECTION.