Bistable device with memory

Claim 1

IN A BISTABLE ELECTRIC CIRCUIT COMPRISING A PAIR OF ELECTRONIC MEMBERS, EACH HAVING AN INPUT, AN OUTPUT AND A CONTROL ELECTRODE; TO CROSS-CONNECTIONS FROM THE OUTPUT ELECTRODE OF ONE MEMBER TO THE CONTROL ELECTRODE OF THE OTHER; AND ELECTRIC BIASSING MEANS CONNECTED TO SAID ELECTRODES IMPARTING THERETO VARIABLE POTENTIAL VALUES, WHEREBY THE CIRCUIT IS CAPABLE OF ASSUMING EITHER OF TWO STABLE CONDITIONS IN WHICH ONE OF THE ELECTRONIC MEMBERS IS CONDUCTIVE AND THE OTHER IS BLOCKED; THE COMBINATION OF A MAGNETIC CORE HAVING A SUBSTANTIALLY RECTANGULAR HYSTERESIS LOOP; A WINDING CARRIED BY SAID CORE AND SERIALLY CONNECTED IN ONE OF SAID CROSS-CONNECTIONS; A VOLTAGE DIVIDER CONNECTED TO SAID BIASING MEANS FOR PROVIDING A SELECTED POTENTIAL INTERMEDIATE THE POTENTIAL VALUES EXISTING AT THE OUTPUT ELECTRODE OF SAID MEMBERS WHEN THE LATTER IS CONDUCTIVE OR BLOCKED; A DIODE CONNECTING THE END OF SAID WINDING REMOTE FROM SAID OUTPUT ELECTRODE TERMINATING THE CORRESPONDING CROSS-CONNECTION TO THE SAID SELECTED POTENTIAL, THE CONDUCTING DIRECTION OF SAID DIODE BEING DIRECTED FROM SAID WINDING END TOWARDS SAID POTENTIAL; A DELAYING NETWORK COMPRISING FIRST RESISTORS SERIALLY CONNECTED IN THE OTHER OF SAID CROSS-CONNECTIONS AND A SHUNT CAPACITOR; AND FURTHER RESISTORS EQUIVALENT TO SAID FIRST RESISTORS SERIALLY CONNECTED IN SAID ONE CROSS-CONNECTION.