Pulse generating circuit comprising pentode, zener diode voltage divider bias means and transistor for controlling pentode output

Claim 1

A PULSE GENERATING CIRCUIT ARRANGEMENT COMPRISING AN OUTPUT TUBE HAVING A CATHODE, AN ANODE AND A CONTROL GRID, AN OUTPUT CIRCUIT INCLUDING SAID CATHODE AND ANODE AN OUTPUT IMPEDANCE IN SAID OUTPUT CIRCUIT, A VOLTAGE DIVIDER NETWORK COMPRISING A REACTANCE FREE IMPEDANCE, MEANS CONNECTING THE CATHODE AND CONTROL ELECTRODE OF SAID OUTPUT TUBE AT TAPPINGS OF SAID NETWORK PROVIDING A BIASING POTENTIAL TO SAID TUBE NORMALLY MAINTAINING THE SAME NONCONDUCTIVE, A TRANSISTOR HAVING EMITTER AND COLLECTOR ELECTRODES FORMING A CURRENT PATH SHUNTING SAID REACTANCE FREE IMPEDANCE AND HAVING AN OUTPUT ELECTRODE, AN ELECTRON DISCHARGE DEVICE HAVING AN OUTPUT ELECTRODE CONNECTED TO SAID BASE ELECTRODE AND FORMING THEREWITH A CURRENT PATH AND HAVING AN INPUT ELECTRODE, MEANS FOR APPLYING A BIASING POTENTIAL TO THE SAID INPUT ELECTRODE OF SAID ELECTRON DISCHARGE DEVICE TO MAINTAIN SAID ELECTRON DISCHARGE DEVICE NORMALLY NONCONDUCTIVE AND TO INTERRUPT THE SAID CURRENT PATH TO THE BASE OF SAID TRANSISTOR, AND MEANS FOR APPLYING TO THE INPUT ELECTRODE OF SAID ELECTRON DISCHARGE DEVICE A PULSE SIGNAL HAVING A POLARITY RENDERING SAID ELECTRON DISCHARGE DEVICE AND SAID TRANSISTOR CONDUCTIVE FOR THE INTERVAL OF SAID PULSE SIGNAL, THE CONDUCTION OF SAID TRANSISTOR DURING THE PULSE INTERVAL BRIDGING SAID REACTANCE FREE IMPEDANCE AND RENDERING SAID OUTPUT TUBE CONDUCTIVE FOR THE INTERVAL OF SAID PULSE SIGNAL.