Marking circuit arrangement having means for suppressing marking potential

Claim 1

A SWITCHING NETWORK OF THE TYPE COMPRISING A PLURALITY OF INPUT TERMINALS, A PLURALITY OF OUTPUT TERMINALS, A PLURALITY OF SWITCHING STAGES EACH HAVING A PLURALITY OF CROSSINGS, AND MEANS INTERCONNECTING SAID INPUT TERMINALS, OUTPUT TERMINALS AND SWITCHING STAGES WHEREBY A PLURALITY OF CHANNELS EXTEND BETWEEN EACH INPUT TERMINAL AND EACH OUTPUT TERMINAL BY WAY OF A CROSSING OF EACH SWITCHING STAGE, WHEREIN EACH CROSSING COMPRISES A BISTABLE ELECTRONIC SWITCH HAVING A MAKING TERMINAL, A PLURALITY OF MARKING WIRES FOR EACH OF SAID STAGES, MEANS CONNECTING EACH MARKING WIRE TO A PLURALITY OF SEPARATE MARKING TERMINALS IN THE RESPECTIVE STAGE, AND MEANS APPLYING MARKING POTENTIALS TO SAID MAKING WIRES; WHEREIN THE IMPROVEMENT COMPRISES A SEPARATE MARKING WIRE, SAID POTENTIAL PRESSING MEANS FOR EACH SAID MARKING WIRE, SAID POTENTIAL SUPPRESSING MEANS COMPRISING MEANS RESPONSIVE TO A CHANGE OF STATE FROM NON-CONDUCTING TO CONDUCTING OF ANY ELECTRONIC SWITCH CONNECTED TO THE MARKING WIRE CONNECTED THERETO FOR PRODUCING A SUPPRESSION POTENTIAL, AND MEANS FOR APPLYING SAID SUPPRESSION POTENTIAL TO THE RESPECTIVE MARKING LINE FOR SUPPRESSING SAID MARKING POTENTIAL, WHEREBY THE DURATION OF APPLICATION OF MARKING POTENTIALS TO SAID MARKING TERMINALS IS MINIMIZED.