Latched carry save adder circuit for multipliers

Claim 1

IN ADDER UNIT FOR GENERATING CONSECUTIVE GROUPS OF SIGNALS REPRESENTING THE SUCCESSIVE PARTIAL PRODUCTS OF A MULTIPLICATION OPERATION, SAID ADDER UNIT COMPRISING: A FIRST CARRY SAVE ADDER HAVING THREE PAIRS OF INPUT SIGNAL LINES FOR ENTERING SIGNALS REPRESENTING THREE OPERANDS TO BE ADDED, EACH DENOMINATIONAL ORDER OF SAID CARRY SAVE ADDER COMPRISING A LATCH CIRCUIT HAVING A PLURALITY OF INPUT COMPONENTS, EACH INPUT COMPONENT RECEIVING A GATE SIGNAL AND A COMBINATION OF AN INPUT SIGNAL LINE FROM EACH PAIR OF THE THREE INPUT SIGNAL LINES FOR SAID DENOMINATIONAL ORDER; A LATCH CONTROL CIRCUIT INITIALLY ACTIVATED BY A CLOCK SIGNAL DURING A SETTING PHASE THEREOF TO GENERATE SAID GATE SIGNAL AND THEREBY TO ENABLE A SELECTED COMBINATION OF INPUT SIGNALS, IF PRESENT, TO PASS THROUGH ONE OF SAID INPUT COMPONENTS TO GENERATE AN OUTPUT SIGNAL; A CIRCUIT CONDUCTING SAID OUTPUT SIGNAL TO SAID LATCH CONTROL CIRCUIT TO MAINTAIN SAID GATE SIGNAL SO LONG AS SAID ONE INPUT COMPONENT RECEIVES ITS SELECTED COMBINATION OF INPUT SIGNALS; A SUM SIGNAL GENERATING CIRCUIT CONTROLLED BY SAID INPUT COMPONENTS TO PROVIDE A SUM SIGNAL WHEN ANY INPUT COMPONENT GENERATES AN OUTPUT SIGNAL AND ANOTHER ELEMENT CONTROLLED BY SAID CLOCK SIGNAL AND SAID SUM SIGNAL GENERATING CIRCUIT TO MAINTAIN THE GENERATING STATE OF SAID SUM SIGNAL GENERATING CIRCUIT DURING THE NON-SETTING PHASE OF SAID CLOCK SIGNAL; EACH DENOMINATIONAL ORDER OF SAID CARRY SAVE ADDER ALSO INCLUDING A SECOND PLURALITY OF INPUT COMPONENTS RECEIVING COMBINATIONS OF SAID INPUT SIGNALS, A SECOND LATCH CONTROL CIRCUIT, A SECOND OUTPUT SIGNAL CONDUCTING CIRCUIT, A SECOND ANOTHER ELEMENT CONTROLLED BY SAID CLOCK SIGNAL AND A CARRY SIGNAL GENERATING CIRCUIT TO PROVIDE A SIGNAL INDICATIVE OF THE PRESENCE OF TWO OR MORE SIGNIFICANT SIGNALS ON SAID INPUT LINES TO SAID DENOMINATIONAL ORDER; A SECOND CARRY SAVE ADDER RECEIVING SAID SUM SIGNALS AND SAID CARRY SIGNALS ON TWO OF ITS INPUTS AND A FOURTH OPERAND ON ITS THIRD INPUT SAID SECOND CARRY SAVE ADDER BEING SETTABLE BY A COMPLEMENTAL CLOCK SIGNAL TO GENERATE A SET OF SECOND SUM SIGNALS AND A SET OF SECOND CARRY SIGNALS AND MEANS CONDUCTING SAID SECOND SET OF SUM OUTPUT SIGNALS TO ONE OPERAND INPUT OF SAID FIRST CARRY SAVE ADDER AND SAID SECOND SET OF CARRY OUTPUT SIGNALS TO A SECOND OPERAND INPUT OF SAID CARRY SAVE ADDER.