Multicell transistor

Claim 1

IN A SEMICONDUCTOR DEVICE: (A) A SEMICONDUCTOR BODY OF A FIRST PREDETERMINED CONDUCTIVITY TYPE DEFINING A SUBSTANTIALLY PLANAR SURFACE; (B) A PLURALITY OF SUBSTANTIALLY IDENTICAL FIRST ELONGATE SURFACE REGIONS OF A SECOND PREDETERMINED CONDUCTIVITY TYPE IN SAID PLANAR SURFACE OF SAID SEMICONDUCTOR BODY, SAID FIRST ELONGATED SURFACE REGIONS BEING DISPOSED TO FORM A CIRCULAR ARRAY AND EQUIDISTANTLY SPACED; (C) A PLURALITY OF SECOND SURFACE REGIONS OF SAID FIRST PREDETERMINED CONDUCTIVITY TYPE, ONE EACH OF SAID SECOND SURFACE REGIONS BEING DISPOSED WITHIN A DIFFERENT ONE OF SAID FIRST SURFACE REGIONS, THE DEPTH OF EACH OF SAID SECOND SURFACE REGIONS BEING LESS THAN THE DEPTH OF THE FIRST SURFACE REGIONS WITHIN WHICH IT IS DISPOSED; (D) A LAYER OF ELECTRICAL INSULATING MATERIAL ESTABLISHED ON SAID PLANAR SURFACE OF SAID SEMICONDUCTOR BODY AND EXPOSING IDENTICAL PORTIONS OF SAID FIRST SURFACE REGIONS; (E) A THIN LAYER OF ELECTROCONDUCTIVE MATERIAL ESTABLISHED IN A PREDETERMINED PATTERN ON SAID LAYER OF ELECTRICAL INSULATING MATERIAL, SAID PREDETERMINED PATTERN DEFINING A DISC SHAPED FIRST PORTION AT THE CENTER OF SAID CIRCULAR ARRAY, AN ANNULAR SECOND PORTION IN OHMIC CONTACT WITH THE EXPOSED IDENTICAL PORTIONS OF SAID FIRST SURFACE REGIONS AND DEFINING A PATH EXTENDING BETWEEN EACH TWO ADJACENT FIRST SURFACE REGIONS, EACH OF SAID PATH BEING OF IDENTICAL LENGTH, AND A PLURALITY OF ELONGATE THIRD PORTIONS OF IDENTICAL LENGTH, EACH OF SAID ELONGATED THIRD PORTIONS INTERCONNECTING SAID DISC SHAPED FIRST PORTION WITH A POINT MIDWAY ON A DIFFERENT ONE OF SAID PATHS DEFINED BY SAID ANNULAR SECOND PORTION BETWEEN TWO ADJACENT FIRST SURFACE REGIONS; AND, (F) MEANS FOR ESTABLISHING ELECTRICAL CONTACT TO THE DISC SHAPED FIRST PORTION OF SAID LAYER OF ELECTROCONDUCTIVE MATERIAL.