Output transistor protecting system in a transistor amplifier circuit

Claim 1

A TRANSISTOR OUTPUT STAGE PROTECTING CIRCUIT SYSTEM IN A SO-CALLED PNP TYPE DARLINGTON-CONNECTED CIRCUIT OF A FUNDAMENTAL FORMATION IN WHICH A LOAD AND AN ELECTRIC SOURCE ARE CONNECTED IN SERIES BETWEEN THE COLLECTOR AND EMITTER OF A PNP TYPE OUTPUT TRANSISTOR TR2, THE COLLECTOR OF A PNP TYPE AMPLIFYING TRANSISTOR TR1 IS CONNECTED TO THE COLLECTOR OF SAID PNP TYPE OUTPUT TRANSISTOR TR2, THE EMITTER OF SAID PNP TYPE AMPLIFYING TRANSISTOR TR1 IS CONNECTED TO THE BASE OF SAID PNP TYPE OUTPUT TRANSISTOR TR2, A SHUNT RESISTOR RB1 IS CONNECTED BETWEEN THE BASE AND EMITTER OF SAID PNP TYPE OUTPUT TRANSISTOR TR2 AND BETWEEN THE BASE OF SAID PNP TYPE AMPLIFYING TRANSISTOR TR1 AND THE EMITTER OF SAID PNP TYPE OUTPUT TRANSISTOR TR2 IS MADE AN INPUT TERMINAL, THE IMPROVEMENT WHICH COMPRISING INSERTING BETWEEN THE COLLECTOR OF SAID PNP TYPE AMPLIFYING TRANSISTOR TR1 AND THE COLLECTOR OF SAID PNP TYPE OUTPUT TRANSISTOR TR2 IN SAID CIRCUIT A PROTECTIVE RESISTOR RS1 OF SUCH VALUE THAT THE VOLTAGE BETWEEN THE EMITTER AND COLLECTOR OF SAID PNP TYPE AMPLIFYING TRANSISTOR TR1 MAY BE SUBSTANTIALLY ZERO WHEN THE MAXIMUM ALLOWABLE CURRENT FLOWS TO SAID PNP TYPE OUTPUT TRANSISTOR TR2 SO THAT SAID PNP TYPE OUTPUT TRANSISTOR TR2 MAY BE PREVENTED FROM BEING DAMAGED BY ANY EXCESS CURRENT IN ITS ABNORMAL OPERATING STATE WITHOUT DIRECTLY LIMITING ITS OUTPUT CURRENT.