US3317820A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage regulator employing variable duty cycle modulating of the unregulated voltage
Assignee: Individual
•
Filing: 1964-03-27
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Granted: 1967-05-02
•
Expires: 1984-03-27
Abstract
No abstract record available.
Inventors
- 👤 Richard A Nylander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 01:09
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155; H02M3/156; H02M3/1563
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
122 words
A VOLTAGE REGULATOR CIRCUIT COMPRISING: A PAIR OF INPUT TERMINALS, BETWEEN WHICH AN UNREGULATED VOLTAGE IS APPLIED, AND A PAIR OF OUTPUT TERMINALS, ONE OF SAID INPUT TERMINALS CONSTITUTING A POINT OF REFERENCE POTENTIAL; A DIRECT CONNECTION OF SUBSTANTIALLY ZERO IMPEDANCE BETWEEN ONE OF SAID OUTPUT TERMINALS AND SAID POINT OF REFERENCE POTENTIAL; A FIRST TRANSISTOR; AN INDUCTIVE REACTOR; A CONDUCTIVE CONNECTION INCLUDING THE EMITTER-COLLECTOR PATH OF SAID FIRST TRANSISTOR AND SAID REACTOR AS SERIES ELEMENTS IN THE ORDER NAMED BETWEEN THE OTHER INPUT TERMINAL AND THE OTHER OUTPUT TERMINAL; A CAPACITIVE REACTOR CONNECTED ACROSS SAID TERMINALS; A RESISTOR AND THE COLLECTOR-EMITTER PATH OF A SECOND TRANSISTOR CONNECTED IN THE ORDER NAMED BETWEEN THE BASE OF SAID FIRST TRANSISTOR AND SAID POINT
Claim 2
Dependent Claim
122 words
A VOLTAGE REGULATOR CIRCUIT COMPRISING: A PAIR OF INPUT TERMINALS, BETWEEN WHICH AN UNREGULATED VOLTAGE IS APPLIED, AND A PAIR OF OUTPUT TERMINALS, ONE OF SAID INPUT TERMINALS CONSTITUTING A POINT OF REFERENCE POTENTIAL; A DIRECT CONNECTION OF SUBSTANTIALLY ZERO IMPEDANCE BETWEEN ONE OF SAID OUTPUT TERMINALS AND SAID POINT OF REFERENCE POTENTIAL; A FIRST TRANSISTOR; AN INDUCTIVE REACTOR; A CONDUCTIVE CONNECTION INCLUDING THE EMITTER-COLLECTOR PATH OF SAID FIRST TRANSISTOR AND SAID REACTOR AS SERIES ELEMENTS IN THE ORDER NAMED BETWEEN THE OTHER INPUT TERMINAL AND THE OTHER OUTPUT TERMINAL; A CAPACITIVE REACTOR CONNECTED ACROSS SAID TERMINALS; A RESISTOR AND THE COLLECTOR-EMITTER PATH OF A SECOND TRANSISTOR CONNECTED IN THE ORDER NAMED BETWEEN THE BASE OF SAID FIRST TRANSISTOR AND SAID POINT
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1970-05-01 | 1970-10-31 | 1971-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1974-05-01 | 1974-10-31 | 1975-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1978-05-01 | 1978-10-31 | 1979-05-02 | $7700.00 | Window Closed / Lapsed |