US3317818A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Regulated power supply
Assignee: Ampex Corp
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Filing: 1963-06-03
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Granted: 1967-05-02
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Expires: 1983-06-03
Abstract
No abstract record available.
Inventors
- 👤 Duane D Beyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:28
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/565; G05F1/567; Y; Y10; Y10S; Y10S323/00; Y10S323/908
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
375 words
A SERIES VOLTAGE REGULATOR COMPRISING FIRST AND SECOND INPUT TERMINALS WHERETO AN UNREGULATED INPUT VOLTAGE IS APPLIED, SAID SECOND INPUT TERMINAL CONNECTED TO GROUND, AN OUTPUT CIRCUIT WHEREACROSS A LOAD IS TO BE CONNECTED AND WHERETO A REGULATED OUTPUT SIGNAL IS SUPPLIED BY SAID REGULATOR, A FIRST TRANSISTOR HAVING A BASE, AN EMITTER AND A COLLECTOR, SAID TRANSISTOR HAVING THE EMITTER-COLLECTOR PATH THEREOF SERIALLY CONNECTED BETWEEN SAID FIRST INPUT TERMINAL AND SAID OUTPUT CIRCUIT AND BEING NORMALLY BIASED IN A CONDUCTIVE STATE BY THE INPUT VOLTAGE APPLIED TO SAID INPUT TERMINALS, A SECOND TRANSISTOR OF OPPOSITE CONDUCTIVITY TYPE TO SAID FIRST TRANSISTOR AND HAVING A BASE, EMITTER AND COLLECTOR, SAID COLLECTOR OF SAID SECOND TRANSISTOR COUPLED TO THE BASE OF SAID FIRST TRANSISTOR, BIAS MEANS COUPLING THE EMITTER-COLLECTOR PATH OF SAID SECOND TRANSISTOR BETWEEN SAID FIRST INPUT TERMINAL AND SAID OUTPUT CIRCUIT TO VARY THE CONDUCTIVITY OF SAID FIRST TRANSISTOR IN DIRECT RELATION TO VARIATIONS IN THE CONDUCTIVITY OF SAID SECOND TRANSISTOR, A THIRD TRANSISTOR OF OPPOSITE CONDUCTIVITY TYPE TO SAID SECOND TRANSISTOR AND HAVING A BASE, EMITTER AND COLLECTOR, SAID COLLECTOR OF SAID THIRD TRANSISTOR COUPLED TO THE BASE OF SAID SECOND TRANSISTOR, BIAS MEANS COUPLING THE EMITTER-COLLECTOR PATH OF SAID THIRD TRANSISTOR BETWEEN SAID FIRST INPUT TERMINAL AND SAID OUTPUT CIRCUIT TO VARY THE CONDUCTIVITY OF SAID SECOND TRANSISTOR IN DIRECT RELATION TO VARIATIONS IN THE CONDUCTIVITY OF SAID THIRD TRANSISTOR, A FOURTH TRANSISTOR OF THE SAME CONDUCTIVITY TYPE AS SAID THIRD TRANSISTOR AND HAVING A BASE, EMITTER AND COLLECTOR, SAID COLLECTOR OF SAID FOURTH TRANSISTOR COUPLED TO THE BASE OF SAID THIRD TRANSISTOR, BIAS MEANS COUPLING SAID COLLECTOR OF SAID FOURTH TRANSISTOR TO SAID FIRST INPUT TERMINAL TO VARY THE CONDUCTIVITY OF SAID THIRD TRANSISTOR IN INVERSE RELATION TO VARIATIONS IN THE CONDUCTIVITY OF SAID FOURTH TRANSISTOR, A ZENER DIODE CONNECTED BETWEEN THE EMITTER OF SAID FOURTH TRANSISTOR AND GROUND, A RESISTOR CONNECTED BETWEEN SAID OUTPUT CIRCUIT AND THE COMMON JUNCTION BETWEEN THE EMITTER OF SAID FOURTH TRANSISTOR AND SAID ZENER DIODE, AND THE PARALLEL COMBINATION OF A CAPACITOR AND SECOND RESISTOR COUPLED BETWEEN SAID OUTPUT CIRCUIT AND THE BASE OF SAID FOURTH TRANSISTOR TO VARY THE CONDUCTIVITY THEREOF IN DIRECT RELATION TO VARIATIONS IN THE VOLTAGE DEVELOPED ACROSS SAID OUTPUT CIRCUIT.
Claim 2
Dependent Claim
375 words
A SERIES VOLTAGE REGULATOR COMPRISING FIRST AND SECOND INPUT TERMINALS WHERETO AN UNREGULATED INPUT VOLTAGE IS APPLIED, SAID SECOND INPUT TERMINAL CONNECTED TO GROUND, AN OUTPUT CIRCUIT WHEREACROSS A LOAD IS TO BE CONNECTED AND WHERETO A REGULATED OUTPUT SIGNAL IS SUPPLIED BY SAID REGULATOR, A FIRST TRANSISTOR HAVING A BASE, AN EMITTER AND A COLLECTOR, SAID TRANSISTOR HAVING THE EMITTER-COLLECTOR PATH THEREOF SERIALLY CONNECTED BETWEEN SAID FIRST INPUT TERMINAL AND SAID OUTPUT CIRCUIT AND BEING NORMALLY BIASED IN A CONDUCTIVE STATE BY THE INPUT VOLTAGE APPLIED TO SAID INPUT TERMINALS, A SECOND TRANSISTOR OF OPPOSITE CONDUCTIVITY TYPE TO SAID FIRST TRANSISTOR AND HAVING A BASE, EMITTER AND COLLECTOR, SAID COLLECTOR OF SAID SECOND TRANSISTOR COUPLED TO THE BASE OF SAID FIRST TRANSISTOR, BIAS MEANS COUPLING THE EMITTER-COLLECTOR PATH OF SAID SECOND TRANSISTOR BETWEEN SAID FIRST INPUT TERMINAL AND SAID OUTPUT CIRCUIT TO VARY THE CONDUCTIVITY OF SAID FIRST TRANSISTOR IN DIRECT RELATION TO VARIATIONS IN THE CONDUCTIVITY OF SAID SECOND TRANSISTOR, A THIRD TRANSISTOR OF OPPOSITE CONDUCTIVITY TYPE TO SAID SECOND TRANSISTOR AND HAVING A BASE, EMITTER AND COLLECTOR, SAID COLLECTOR OF SAID THIRD TRANSISTOR COUPLED TO THE BASE OF SAID SECOND TRANSISTOR, BIAS MEANS COUPLING THE EMITTER-COLLECTOR PATH OF SAID THIRD TRANSISTOR BETWEEN SAID FIRST INPUT TERMINAL AND SAID OUTPUT CIRCUIT TO VARY THE CONDUCTIVITY OF SAID SECOND TRANSISTOR IN DIRECT RELATION TO VARIATIONS IN THE CONDUCTIVITY OF SAID THIRD TRANSISTOR, A FOURTH TRANSISTOR OF THE SAME CONDUCTIVITY TYPE AS SAID THIRD TRANSISTOR AND HAVING A BASE, EMITTER AND COLLECTOR, SAID COLLECTOR OF SAID FOURTH TRANSISTOR COUPLED TO THE BASE OF SAID THIRD TRANSISTOR, BIAS MEANS COUPLING SAID COLLECTOR OF SAID FOURTH TRANSISTOR TO SAID FIRST INPUT TERMINAL TO VARY THE CONDUCTIVITY OF SAID THIRD TRANSISTOR IN INVERSE RELATION TO VARIATIONS IN THE CONDUCTIVITY OF SAID FOURTH TRANSISTOR, A ZENER DIODE CONNECTED BETWEEN THE EMITTER OF SAID FOURTH TRANSISTOR AND GROUND, A RESISTOR CONNECTED BETWEEN SAID OUTPUT CIRCUIT AND THE COMMON JUNCTION BETWEEN THE EMITTER OF SAID FOURTH TRANSISTOR AND SAID ZENER DIODE, AND THE PARALLEL COMBINATION OF A CAPACITOR AND SECOND RESISTOR COUPLED BETWEEN SAID OUTPUT CIRCUIT AND THE BASE OF SAID FOURTH TRANSISTOR TO VARY THE CONDUCTIVITY THEREOF IN DIRECT RELATION TO VARIATIONS IN THE VOLTAGE DEVELOPED ACROSS SAID OUTPUT CIRCUIT.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1970-05-01 | 1970-10-31 | 1971-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1974-05-01 | 1974-10-31 | 1975-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1978-05-01 | 1978-10-31 | 1979-05-02 | $7700.00 | Window Closed / Lapsed |