Frequency division timing circuit employing shunting circuit for inhibiting false reset signals to flip-flop stages

Claim 1

IN A FREQUENCY DIVISION TIMING CIRCUIT INCLUDING A MASTER GENERATOR, PLURAL FLIP-FLOP STAGES CONNECTED IN SERIES TO SAID MASTER GENERATOR TO DIVIDE THE FREQUENCY OF THE LATTER TO PROVIDE PREDETERMINED TIMED PERIODS, DIFFERENTIATING MEANS, A RE-SET LINE COMMONLY CONNECTING SAID DIFFERENTIATING MEANS TO SAID FLIP-FLOP STAGES FOR RE-SETTING OF THE LATTER TO AN INITIAL POSITION, AND SWITCH MEANS OPERABLE, WHEN CLOSED, TO CONNECT SAID MASTER GENERATOR AND SAID DIFFERENTIATING MEANS TO A CURRENT SOURCE WHICH IS ALSO CONNECTED TO SUPPLY OTHER LOADS, SAID DIFFERENTIATING MEANS DIFFERENTIATING THE INITIAL VOLTAGE SURGE, APPEARING RESPONSIVE TO CLOSURE OF SAID SWITCH MEANS, TO APPLY A RE-SET PULSE TO SAID RE-SET LINE; ELECTRONIC MEANS OPERABLE TO PREVENT RE-SETTING OF SAID STAGES BY A SPURIOUS PULSE FROM SAID DIFFERENTIATING MEANS RESULTING FROM SHARP CHANGES IN THE LOAD ON SAID COMMON SOURCE DRAWN BY SAID OTHER LOADS, SAID ELECTRONIC MEANS COMPRISING, IN COMBINATION, CIRCUIT COMPONENTS CONNECTED TO SAID RE-SET LINE BETWEEN SAID FLIPFLOP STAGES AND SAID SWITCH MEANS AND SHUNTING SAID DIFFERENTIATING MEANS, SAID CIRCUIT COMPONENTS BEING OPERATIVE TO SHUNT SAID SPURIOUS OR FALSE RE-SET PULSES TO INHIBIT FALSE RE-SETTING OF SAID FLIP-FLOP STAGES; AND A TIME DELAY MEANS INCLUDED IN SAID CIRCUIT COMPONENTS, SAID TIME DELAY MEANS BEING OPERATIVE, IN RESPONSE TO CLOSURE OF SAID SWITCH MEANS, TO EFFECTIVELY DELAY OPERATION OF SAID COMPONENTS FOR A PREDETERMINED TIME PERIOD EQUAL TO A RE-SET PULSE, WHEREBY RE-SETTING OF SAID FLIP-FLOP STAGES MAY TAKE PLACE DURING A NORMAL RE-SET OPERATION.