Noise reduction circuit for a binary signal discriminator

Claim 1

IN A MAGNETIC MEMORY SYSTEM WHICH IS ADAPTED ON APPROPRIATE ADDRESSING TO PRODUCE BINARY ONE AND ZERO SIGNALS OF DIFFERENT CONFIGURATION IN A SENSING CIRCUIT INCLUDED IN SAID MEMORY SYSTEM, EACH SUCH SIGNAL EXTENDING OVER A PREDETERMINED BIT INTERVAL OF TIME, AN AMPLIFIER, A SOURCE OF CLOCK PULSE SIGNALS CONTROLLING THE OPERATION OF SAID MEMORY SYSTEM, A RESISTOR AND A CAPACITOR CONNECTED IN A SERIES CIRCUIT IN THE OUTPUT OF SAID AMPLIFIER, A NORMALLY-CONDUCTING CLAMP CIRCUIT CONNECTED IN SERIES WITH SAID RESISTOR AND CAPACITOR FOR CONNECTING SAID SERIES CIRCUIT ACROSS THE OUTPUT OF SAID AMPLIFIER WHEN SAID CLAMP IS CONDUCTING, MEANS APPLYING SAID CLOCK PULSE SIGNALS TO BIAS SAID CLAMP NONCONDUCTING AT A TIME T1 AFTER THE START OF EACH OF SAID BIT INTERVALS AND FOR A PREDETERMINED TIME AFTER SAID TIME T1, DETECTOR MEANS CONNECTED ACROSS SAID CLAMP AND ADAPTED TO BE ACTUATED AT A TIME T2 BY SAID CLOCK PULSES WHEN SAID CLAMP IS NONCONDUCTING, AND THE IMPEDANCES OF SAID RESISTOR AND CAPACITOR BEING PROPORTIONED TO HAVE A TIME CONSTANT SUCH THAT THE CHARGE VOLTAGE ACCUMULATED ON SAID CAPACITOR AT TIME T1 IS SUBSTANTIALLY EQUAL TO THE MAGNITUDE OF A BINARY ZERO SIGNAL AT SAID TIME T2.