← Back to Patent Explorer
US3304468A Expired / Lapsed US ⏱️ 0.0 years remaining

Replaceable electronic module for master circuit boards

Assignee: General Electric Co
•
Filing: 1965-05-05
•
Granted: 1967-02-14
•
Expires: 1985-05-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

No abstract record available.

Inventors

  • 👤 Alfred C Lawson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 04:06
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/145

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 182 words
A CIRCUIT MODULE ADAPTED FOR MOUNTING ON A CIRCUIT BOARD COMPRISING: (A) FIRST AND SECOND SPACED, PARALLEL CIRCUIT WAFERS, EACH CIRCUIT WAFER HAVING MEANS FORMED THEREON TO TRAP A CONDUCTOR AND CONDUCTIVE MEANS FORMED ON EACH OF SAID WAFERS; (B) A PLURALITY OF ELECTRICAL COMPONENTS DISPOSED BETWEEN SAID CIRCUIT WAFERS WITH TERMINAL PORTIONS OF EACH OF SAID ELECTRICAL COMPONENTS HELD BY SAID TRAPPING MEANS; (C) A PLURALITY OF CONNECTOR POSTS PARTIALLY DISPOSED BETWEEN SAID CIRCUIT WAFERS AND IN SAID TRAPPING MEANS, EACH OF SAID CONNECTOR POST HAVING A FIRST END PORTION EXTENDING BEYOND SAID FIRST CIRCUIT WAFER AND CONSTITUTING THE SOLE MEANS FOR CONNECTING SAID MODULE TO THE CIRCUIT BOARD AND A SECOND END PORTION TERMINATING ADJACENT SAID SECOND CIRCUIT WAFER; (D) MEANS CONNECTING ONLY THOSE TERMINAL PORTIONS HELD BY SAID TRAPPING MEANS FORMED ON SAID FIRST CIRCUIT WAFER TO SAID CONDUCTIVE MEANS THEREON; AND (E) MEANS CONNECTING SAID TERMINAL PORTIONS AND SAID CONNECTOR POST SECOND END PORTIONS TO SAID CONDUCTIVE MEANS FORMED ON SAID SECOND CIRCUIT WAFER, ONLY SAID CONNECTOR POST SECOND END PORTION BEING PERMANENTLY CONNECTED TO SAID CIRCUIT MODULE.
Claim 2
Dependent Claim 182 words
A CIRCUIT MODULE ADAPTED FOR MOUNTING ON A CIRCUIT BOARD COMPRISING: (A) FIRST AND SECOND SPACED, PARALLEL CIRCUIT WAFERS, EACH CIRCUIT WAFER HAVING MEANS FORMED THEREON TO TRAP A CONDUCTOR AND CONDUCTIVE MEANS FORMED ON EACH OF SAID WAFERS; (B) A PLURALITY OF ELECTRICAL COMPONENTS DISPOSED BETWEEN SAID CIRCUIT WAFERS WITH TERMINAL PORTIONS OF EACH OF SAID ELECTRICAL COMPONENTS HELD BY SAID TRAPPING MEANS; (C) A PLURALITY OF CONNECTOR POSTS PARTIALLY DISPOSED BETWEEN SAID CIRCUIT WAFERS AND IN SAID TRAPPING MEANS, EACH OF SAID CONNECTOR POST HAVING A FIRST END PORTION EXTENDING BEYOND SAID FIRST CIRCUIT WAFER AND CONSTITUTING THE SOLE MEANS FOR CONNECTING SAID MODULE TO THE CIRCUIT BOARD AND A SECOND END PORTION TERMINATING ADJACENT SAID SECOND CIRCUIT WAFER; (D) MEANS CONNECTING ONLY THOSE TERMINAL PORTIONS HELD BY SAID TRAPPING MEANS FORMED ON SAID FIRST CIRCUIT WAFER TO SAID CONDUCTIVE MEANS THEREON; AND (E) MEANS CONNECTING SAID TERMINAL PORTIONS AND SAID CONNECTOR POST SECOND END PORTIONS TO SAID CONDUCTIVE MEANS FORMED ON SAID SECOND CIRCUIT WAFER, ONLY SAID CONNECTOR POST SECOND END PORTION BEING PERMANENTLY CONNECTED TO SAID CIRCUIT MODULE.

References Cited (Backward Citations)

FR1275263A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1970-02-13 1970-08-15 1971-02-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1974-02-13 1974-08-15 1975-02-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1978-02-13 1978-08-15 1979-02-14 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag