Flexible logic circuits for buffer memory

Claim 1

IN COMBINATION IN A CONTROL SYSTEM FOR FEEDING ASYNCHRONOUS EVENT WORDS OF BINARY BITS INTO A SYNCHRONOUS COMPUTER MEMORY, A BUFFER MEMORY WITH WRITE-IN MEANS AND READ-OUT MEANS COUPLED, RESPECTIVELY, TO THE SOURCE OF EVENT WORDS AND TO SAID COMPUTER MEMORY, A WRITE ADDRESS COUNTER FOR ROUTING SUCCESSIVE EVENT WORDS TO DIFFERENT ADDRESSES IN SAID BUFFER MEMORY, A READ ADDRESS COUNTER FOR SUCCESSIVELY TRANSFERRING EVENT WORDS OUT OF DIFFERENT ADDRESSES OF SAID MEMORY TO SAID COMPUTER MEMORY, SAID WRITE ADDRESS AND READ ADDRESS COUNTERS EACH COMPRISING CASCADED BISTABLE BINARY STAGES WITH COMPLEMENTARY OUTPUT TERMINALS, LOGICAL CIRCUIT MEANS FOR ADDING A BINARY ONE TO THE WRITE ADDRESS COUNTER NUMBER AND LOGICAL CIRCUIT MEANS FOR COMPARING THE AUGMENTED WRITE ADDRESS NUMBER WITH THE READ ADDRESS COUNTER NUMBER, AND CIRCUIT MEANS FOR INHIBITING READ-OUT OF EVENT WORDS FROM THE BUFFER MEMORY WHILE THE COMPARED NUMBERS ARE EQUAL TO KEEP THE READ-OUT OPERATION ALWAYS AT LEAST ONE ADDRESS BEHIND THE WRITE-IN OPERATION.