Sequential bit binary detector circuit and system

Claim 1

IN A SYSTEM FOR PRODUCING A TIMED OUTPUT, THE COMBINATION COMPRISING A SOURCE OF CLOCK PULSES, A MAXIMAL FEEDBACK SHIFT REGISTER FOR GENERATING CYCLES OF BINARY CODES WITH EACH CODE BEING COMPRISED OF A SERIES OF DISTINCT BINARY CODE PATTERNS OF EQUAL BIT LENGTH AND WITH EACH PATTERN GENERATED RESPONSIVE TO A PULSE FROM SAID SOURCE, A COUNTER DETECTOR COMPRISED OF A NUMBER OF BISTABLE STAGES DRIVEN BY SAID SOURCE, SAID COUNTER DETECTOR INCLUDING AN OUTPUT LEAD ENERGIZED BY THE PRESENCE OF A BINARY ONE IN THE LAST STAGE THEREOF, A CLEAR RESET DRIVER CONNECTED TO SAID MAXIMAL FEEDBACK SHIFT REGISTER AND DRIVEN THEREBY TO PREVENT THE PRESENCE OF A BINARY ONE IN THE LAST STAGE OF SAID COUNTER DETECTOR RESPONSIVE TO EACH BINARY ONE SUPPLIED TO SAID COUNTER DETECTOR FROM SAID MAXIMAL FEEDBACK SHIFT REGISTER, WHEREBY THE CODE PATTERNS GENERATED BY SAID MAXIMAL FEEDBACK SHIFT REGISTER DRIVE SAID COUNTER DETECTOR TO PRODUCE A DETECT OUTPUT SIGNAL ONCE PER CODE CYCLE.