Memory circuit for indicator devices employing four-electrode, four-layer semiconductor switch

Claim 1

A CIRCUIT FOR OPERATING INDICATOR DEVICES COMPRISING AN INDICATOR TUBE INCLUDING A GAS-FILLED ENVELOPE WHICH CONTAINS AN ANODE ELECTRODE AND A PLURALITY OF CATHODE INDICATOR ELECTRODES, EACH OF WHICH PROVIDES A VISUAL CHARACTER INDICATION, A MULTIPLE JUNCTION SEMICONDUCTOR SWITCHING DEVICE INCLUDING FIRST, SECOND, THIRD, AND FOURTH ZONES OF PTYPE AND N-TYPE SEMICONDUCTOR MATERIAL WHICH ALTERNATE IN CONDUCTIVITY, TYPE WITH A P-N JUNCTION BETWEEN ADJACENT ZONES, SAID FIRST ZONE COMPRISING AN ANODE, SAID SECOND ZONE COMPRISING AN ANODE GATE, SAID THIRD ZONE COMPRISING A CATHODE GATE, AND SAID FOURTH ZONE COMPRISING A CATHODE, SAID FIRST ZONE BEING CONNECTED TO A SOURCE OF RELATIVELY LOW BIAS VOLTAGE, SAID SECOND ZONE BEING CONNECTED BOTH TO ONE OF SAID INDICATOR ELECTRODES IN SAID TUBE AND THROUGH A RESISTOR TO A SOURCE OF RELATIVELY HIGH BIAS VOLTAGE, SAID FOURTH ZONE BEING COUPLED TO A SOURCE OF CONTROL SIGNALS FOR TURNING THE SEMICONDUCTOR DEVICE OFF AND ON, AND SAID THIRD ZONE BEING COUPLED TO A SOURCE OF SIGNAL INFORMATION, THE ENTRY OF WHICH IN SAID INDICATOR TUBE IS CONTROLLED BY SAID CONTROL SIGNALS.