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US3289088A Expired / Lapsed US ⏱️ 0.0 years remaining

Automatic non-linear gain control circuit

Assignee: Individual
•
Filing: 1963-05-29
•
Granted: 1966-11-29
•
Expires: 1983-05-29
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Abstract

No abstract record available.

Inventors

  • 👤 Gerald M Berger

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 23:30
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3052; H03G3/3063; H03G1/00; H03G1/0005; H03G1/0035; H03G1/0082

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 269 words
IN A SIGNAL TRANSLATION SYSTEM HAVING AN ELECTRONICALLY CONTROLLED VARIABLE RESISTANCE FOR CONTROLLING AN INPUT SIGNAL TO AN INTERMEDIATE FREQUENCY AMPLIFIER STAGE FOR PROVIDING A LOGARITHMIC OUTPUT VOLTAGE COMPRISING: FIRST AND SECOND INPUT TERMINALS, A SIGNAL VOLTAGE APPLIED TO SAID TERMINALS, A FIRST TRANSISTOR HAVING BASE, COLLECTOR AND EMITTER ELEMENTS, A FIXED EMITTER RESISTANCE COUPLED FROM THE FIRST TRANSISTOR EMITTER ELEMENT TO GROUND POTENTIAL, COUPLING CAPACITOR COUPLED BETWEEN THE FIRST OF SAID INPUT TERMINALS AND SAID COLLECTOR ELEMENT, SAID INPUT SIGNAL COUPLED VIA THE COUPLING CAPACITOR TO THE FIRST TRANSISTOR COLLECTOR ELEMENT FOR PROVIDING THE SIGNAL VOLTAGE ACROSS THE FIRST TRANSISTOR COLLECTOREMITTER AND SAID FIXED EMITTER RESISTANCE, SAID FIXED EMITTER RESISTANCE BEING COUPLED TO THE INPUT OF SAID INTERMEDIATE FREQUENCY AMPLIFIER FOR PROVIDING AMPLIFICATION OF SAID SIGNAL VOLTAGE, A DETECTION STAGE COUPLED TO THE OUTPUT OF THE SAID INTERMEDIATE FREQUENCY AMPLIFIER FOR DEMODULATING THE SIGNAL INPUT VOLTAGE, A SECOND TRANSISTOR HAVING BASE, EMITTER AND COLLECTOR ELEMENTS, AND MEANS FOR COUPLING A CONTROL VOLTAGE DEVELOPED IN SAID DETECTION STAGE TO THE BASE OF THE SECOND TRANSISTOR, SAID EMITTER OF THE SECOND TRANSISTOR COUPLED THROUGH A RESISTOR DIODE CIRCUIT TO GROUND POTENTIAL, SAID RESISTOR DIODE CIRCUIT DEVELOPING A BIAS CURRENT FOR CONTROLLING THE IMPEDANCE OF SAID FIRST TRANSISTOR, AND MEANS FOR COUPLING THE BIAS CURRENT TO THE BASE OF SAID FIRST TRANSISTOR, WHEREBY THE INPUT SIGNAL VOLTAGE APPEARING ACROSS THE EMITTER-COLLECTOR OF THE FIRST TRANSISTOR AND THE FIXED RESISTOR IS ATTENUATED IN RESPONSE TO THE VARIATION OF THE BIAS CURRENT DEVELOPED IN THE RESISTOR DIODE CIRCUIT THEREBY PROVIDING AN OUTPUT SIGNAL VARIED IN ACCORDANCE WITH THE VARIATION OF THE BIAS CURRENT.
Claim 2
Dependent Claim 269 words
IN A SIGNAL TRANSLATION SYSTEM HAVING AN ELECTRONICALLY CONTROLLED VARIABLE RESISTANCE FOR CONTROLLING AN INPUT SIGNAL TO AN INTERMEDIATE FREQUENCY AMPLIFIER STAGE FOR PROVIDING A LOGARITHMIC OUTPUT VOLTAGE COMPRISING: FIRST AND SECOND INPUT TERMINALS, A SIGNAL VOLTAGE APPLIED TO SAID TERMINALS, A FIRST TRANSISTOR HAVING BASE, COLLECTOR AND EMITTER ELEMENTS, A FIXED EMITTER RESISTANCE COUPLED FROM THE FIRST TRANSISTOR EMITTER ELEMENT TO GROUND POTENTIAL, COUPLING CAPACITOR COUPLED BETWEEN THE FIRST OF SAID INPUT TERMINALS AND SAID COLLECTOR ELEMENT, SAID INPUT SIGNAL COUPLED VIA THE COUPLING CAPACITOR TO THE FIRST TRANSISTOR COLLECTOR ELEMENT FOR PROVIDING THE SIGNAL VOLTAGE ACROSS THE FIRST TRANSISTOR COLLECTOREMITTER AND SAID FIXED EMITTER RESISTANCE, SAID FIXED EMITTER RESISTANCE BEING COUPLED TO THE INPUT OF SAID INTERMEDIATE FREQUENCY AMPLIFIER FOR PROVIDING AMPLIFICATION OF SAID SIGNAL VOLTAGE, A DETECTION STAGE COUPLED TO THE OUTPUT OF THE SAID INTERMEDIATE FREQUENCY AMPLIFIER FOR DEMODULATING THE SIGNAL INPUT VOLTAGE, A SECOND TRANSISTOR HAVING BASE, EMITTER AND COLLECTOR ELEMENTS, AND MEANS FOR COUPLING A CONTROL VOLTAGE DEVELOPED IN SAID DETECTION STAGE TO THE BASE OF THE SECOND TRANSISTOR, SAID EMITTER OF THE SECOND TRANSISTOR COUPLED THROUGH A RESISTOR DIODE CIRCUIT TO GROUND POTENTIAL, SAID RESISTOR DIODE CIRCUIT DEVELOPING A BIAS CURRENT FOR CONTROLLING THE IMPEDANCE OF SAID FIRST TRANSISTOR, AND MEANS FOR COUPLING THE BIAS CURRENT TO THE BASE OF SAID FIRST TRANSISTOR, WHEREBY THE INPUT SIGNAL VOLTAGE APPEARING ACROSS THE EMITTER-COLLECTOR OF THE FIRST TRANSISTOR AND THE FIXED RESISTOR IS ATTENUATED IN RESPONSE TO THE VARIATION OF THE BIAS CURRENT DEVELOPED IN THE RESISTOR DIODE CIRCUIT THEREBY PROVIDING AN OUTPUT SIGNAL VARIED IN ACCORDANCE WITH THE VARIATION OF THE BIAS CURRENT.

References Cited (Backward Citations)

US2877348A Cited
US3030504A Cited
US3108197A Cited
US3172040A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1969-11-28 1970-05-30 1970-11-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1973-11-28 1974-05-30 1974-11-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1977-11-28 1978-05-30 1978-11-29 $7700.00 Window Closed / Lapsed

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