Logic circuits employing torsionally strained magnetic cores

Claim 1

A MULTI-STAGE LOGIC CIRCUIT COMPRISING A FIRST STAGE INCLUDING A FIRST SATURABLE CORE LINEARLY DISPOSED, MEANS APPLYING A TORSIONAL STRAIN TO SAID FIRST CORE, A FIRST INPUT CIRCUIT INCLUDING INPUT WINDING MEANS ON SAID FIRST CORE, A FIRST READOUT WINDING ON SAID FIRST CORE, A FIRST RESET WINDING ON SAID FIRST CORE, A SECOND STAGE INCLUDING A SECOND SATURABLE CORE LINEARLY DISPOSED MEANS APPLYING A TORSIONAL STRAIN TO SAID SECOND CORE, A SECOND INPUT CIRCUIT INCLUDING INPUT WINDING MEANS ON SAID SECOND CORE, A SECOND READOUT WINDING ON SAID SECOND CORE, A SECOND RESET WINDING ON SAID SECOND CORE, MEANS CONNECTING SAID INPUT CIRCUIT TO A SOURCE OF SIGNAL OUTPUT VOLTAGE FROM A PREVIOUS STAGE OF SAID LOGIC CIRCUIT, MEANS SERIALLY INTERCONNECTING SAID FIRST READOUT WINDING AND SAID SECOND RESET WINDING TO A FIRST SOURCE OF READOUT CURRENT PULSES WHEREBY A CURRENT PULSE FROM SAID FIRST SOURCE MAY RESET SAID SECOND CORE, MEANS CONNECTING SAID FIRST READOUT WINDING TO SAID SECOND INPUT CIRCUIT WHEREBY AN OUTPUT VOLTAGE FROM SAID FIRST READOUT WINDING MAY SUPPLY AN UNPUT VOLTAGE PULSE TO SAID SECOND UNPUT CIRCUIT, SAID FIRST RESET WINDING AND SAID SECOND READOUT WINDING SERIALLY