US3280346A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse circuit generating noise discriminated time-reference pulses from analog input
Assignee: International Business Machines Corp
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Filing: 1964-04-06
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Granted: 1966-10-18
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Expires: 1984-04-06
Abstract
No abstract record available.
Inventors
- 👤 Schoute Johannes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:08
CPC Classifications
H; H03; H03K; H03K5/00; G; G06; G06V; G06V10/00; G06V10/20; G06V10/28; H03K5/153
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
327 words
A CIRCUIT ARRANGEMENT FOR PRODUCING A TIME REFERENCE PULSE IN RESPONSE TO AN INPUT PULSE VARYING IN AMPLITUDE AND SHAPE COMPRISING. A PAIR OF CAPACITORS, EACH HAVING TWO ELECTRODES, MEANS CONNECTING ONE OF SAID ELECTRODES OF EACH OF SAID CAPACITORS TO A POINT OF FIXED REFERENCE POTENTIAL, TWO PAIRS OF TRANSISTORS, EACH TRANSISTOR HAVING EMITTER, BASE AND COLLECTOR ELECTRODES, MEANS CONNECTING THE EMITTER ELECTRODES OF BOTH OF SAID TRANSISTORS OF EACH PAIR TO THE OTHER ELECTRODE OF ONE OF SAID CAPACITORS, MEANS APPLYING DIRECT ENERGIZING POTENTIAL TO THE COLLECTOR ELECTRODES OF SAID TRANSISTORS, AN ATTENUATOR HAVING INPUT AND OUTPUT TERMINALS, MEANS FOR APPLYING AN INPUT PULSE SIGNAL TO THE INPUT TERMINAL OF SAID ATTENUATOR FOR DERIVING A PREDETERMINED FRACTION OF SAID INPUT PULSE SIGNAL AT THE OUTPUT TERMINAL OF SAID ATTENUATOR, MEANS CONNECTING THE OUTPUT TERMINAL OF SAID ATTENUATOR TO THE BASE ELECTRODE OF ONE OF SAID TRANSISTORS OF EACH PAIR FOR CHARGING THE CORRESPONDING CAPACITOR ON THE LEADING EDGE OF SAID INPUT PULSE TO A VALUE SUBSTANTIALLY EQUAL TO SAID PREDETERMINED FRACTION OF THE PEAK VOLTAGE OF SAID INPUT PULSE SIGNAL AT WHICH VALUE SAID ONE TRANSISTOR OF EACH PAIR CEASES CONDUCTING, MEANS FOR DELAYING SAID INPUT PULSE SIGNAL, SIGNAL TO THE OTHER TRANSISTOR OF ONE OF SAID PAIRS OF TRANSISTORS AT WHICH SAID OTHER TRANSISTOR BEGINS TO CONDUCT AT THE VALUE OF SAID INPUT SIGNAL EQUALING THE CHARGE ON THE ONE CAPACITOR CORRESPONDING TO SAID ONE PAIR OF TRANSISTORS, AN OR GATE HAVING TWO INPUT TERMINALS AND AN OUTPUT TERMINAL, MEANS CONNECTING ONE INPUT TERMINAL OF SAID OR GATE TO THE OTHER ELECTRODE OF SAID ONE CAPACITOR, MEANS APPLYING THRESHOLDING POTENTIAL TO THE OTHER INPUT TERMINAL OF SAID OR GATE, MEANS CONNECTING THE OUTPUT TERMINAL OF SAID OR GATE TO THE BASE ELECTRODE OF THE OTHER TRANSISTOR OF THE OTHER PAIR OF TRANSISTORS, AND MEANS FOR DERIVING A PULSE AT THE COLLECTOR ELECTRODE OF SAID OTHER TRANSISTOR INDICATIVE OF THE TIMING OF SAID INPUT PULSE.
Claim 2
Dependent Claim
327 words
A CIRCUIT ARRANGEMENT FOR PRODUCING A TIME REFERENCE PULSE IN RESPONSE TO AN INPUT PULSE VARYING IN AMPLITUDE AND SHAPE COMPRISING. A PAIR OF CAPACITORS, EACH HAVING TWO ELECTRODES, MEANS CONNECTING ONE OF SAID ELECTRODES OF EACH OF SAID CAPACITORS TO A POINT OF FIXED REFERENCE POTENTIAL, TWO PAIRS OF TRANSISTORS, EACH TRANSISTOR HAVING EMITTER, BASE AND COLLECTOR ELECTRODES, MEANS CONNECTING THE EMITTER ELECTRODES OF BOTH OF SAID TRANSISTORS OF EACH PAIR TO THE OTHER ELECTRODE OF ONE OF SAID CAPACITORS, MEANS APPLYING DIRECT ENERGIZING POTENTIAL TO THE COLLECTOR ELECTRODES OF SAID TRANSISTORS, AN ATTENUATOR HAVING INPUT AND OUTPUT TERMINALS, MEANS FOR APPLYING AN INPUT PULSE SIGNAL TO THE INPUT TERMINAL OF SAID ATTENUATOR FOR DERIVING A PREDETERMINED FRACTION OF SAID INPUT PULSE SIGNAL AT THE OUTPUT TERMINAL OF SAID ATTENUATOR, MEANS CONNECTING THE OUTPUT TERMINAL OF SAID ATTENUATOR TO THE BASE ELECTRODE OF ONE OF SAID TRANSISTORS OF EACH PAIR FOR CHARGING THE CORRESPONDING CAPACITOR ON THE LEADING EDGE OF SAID INPUT PULSE TO A VALUE SUBSTANTIALLY EQUAL TO SAID PREDETERMINED FRACTION OF THE PEAK VOLTAGE OF SAID INPUT PULSE SIGNAL AT WHICH VALUE SAID ONE TRANSISTOR OF EACH PAIR CEASES CONDUCTING, MEANS FOR DELAYING SAID INPUT PULSE SIGNAL, SIGNAL TO THE OTHER TRANSISTOR OF ONE OF SAID PAIRS OF TRANSISTORS AT WHICH SAID OTHER TRANSISTOR BEGINS TO CONDUCT AT THE VALUE OF SAID INPUT SIGNAL EQUALING THE CHARGE ON THE ONE CAPACITOR CORRESPONDING TO SAID ONE PAIR OF TRANSISTORS, AN OR GATE HAVING TWO INPUT TERMINALS AND AN OUTPUT TERMINAL, MEANS CONNECTING ONE INPUT TERMINAL OF SAID OR GATE TO THE OTHER ELECTRODE OF SAID ONE CAPACITOR, MEANS APPLYING THRESHOLDING POTENTIAL TO THE OTHER INPUT TERMINAL OF SAID OR GATE, MEANS CONNECTING THE OUTPUT TERMINAL OF SAID OR GATE TO THE BASE ELECTRODE OF THE OTHER TRANSISTOR OF THE OTHER PAIR OF TRANSISTORS, AND MEANS FOR DERIVING A PULSE AT THE COLLECTOR ELECTRODE OF SAID OTHER TRANSISTOR INDICATIVE OF THE TIMING OF SAID INPUT PULSE.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1969-10-17 | 1970-04-18 | 1970-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1973-10-17 | 1974-04-18 | 1974-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1977-10-17 | 1978-04-18 | 1978-10-18 | $7700.00 | Window Closed / Lapsed |