US3277312A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential response circuit
Assignee: Singer Co
•
Filing: 1963-07-03
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Granted: 1966-10-04
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Expires: 1983-07-03
Abstract
No abstract record available.
Inventors
- 👤 William C Harris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:14
CPC Classifications
G; G08; G08B; G08B13/00; G08B13/22; H; H03; H03K; H03K17/00; H03K17/30
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
154 words
A CIRCUIT FOR PRODUCING AN OUTPUT SIGNAL RESPONSIVELY TO A PREDETERMINED DIFFERENCE BETWEEN TWO INPUT SIGNALS COMPRISING A FULL-WAVE DIODE BRIDGE RECTIFIER HAVING A PAIR OF DIAMETRICALLY OPPOSED INPUT TERMINALS AND A PAIR OF DIAMETRICALLY OPPOSED OUTPUT TERMINALS, MEANS CONNECTING SAID INPUT SIGNALS IN SERIES OPPOSITION DIRECTLY ACROSS SAID PAIR OF INPUT TERMINALS, A TRANSISTOR HAVING A BASE, AN EMITTER, AND A COLLECTOR, SAID BASE AND SAID EMITTER EACH BEING CONNECTED DIRECTLY TO A RESPECTIVE ONE OF SAID OUTPUT TERMINALS, A POWER SOURCE HAVING A COMMON CONNECTION WITH EACH OF SAID INPUT SIGNALS, A LOAD IMPEDANCE CONNECTED IN SERIES WITH THE COLLECTOR AND THE END OF SAID POWER VOLTAGE SOURCE OPPOSITE TO SAID COMMON CONNECTION END, A RESISTOR CONNECTED BETWEEN SAID COMMON CONNECTION AND THE EMITTER OF THE TRANSISTOR AND MEANS FOR BIASING SAID TRANSISTOR TO ESTABLISH A PREDETERMINED QUIESCENT CURRENT IN SAID LOAD IMPEDANCE WHEN SAID INPUT SIGNALS ARE OF SUBSTANTIALLY EQUAL VALUES.
Claim 2
Dependent Claim
154 words
A CIRCUIT FOR PRODUCING AN OUTPUT SIGNAL RESPONSIVELY TO A PREDETERMINED DIFFERENCE BETWEEN TWO INPUT SIGNALS COMPRISING A FULL-WAVE DIODE BRIDGE RECTIFIER HAVING A PAIR OF DIAMETRICALLY OPPOSED INPUT TERMINALS AND A PAIR OF DIAMETRICALLY OPPOSED OUTPUT TERMINALS, MEANS CONNECTING SAID INPUT SIGNALS IN SERIES OPPOSITION DIRECTLY ACROSS SAID PAIR OF INPUT TERMINALS, A TRANSISTOR HAVING A BASE, AN EMITTER, AND A COLLECTOR, SAID BASE AND SAID EMITTER EACH BEING CONNECTED DIRECTLY TO A RESPECTIVE ONE OF SAID OUTPUT TERMINALS, A POWER SOURCE HAVING A COMMON CONNECTION WITH EACH OF SAID INPUT SIGNALS, A LOAD IMPEDANCE CONNECTED IN SERIES WITH THE COLLECTOR AND THE END OF SAID POWER VOLTAGE SOURCE OPPOSITE TO SAID COMMON CONNECTION END, A RESISTOR CONNECTED BETWEEN SAID COMMON CONNECTION AND THE EMITTER OF THE TRANSISTOR AND MEANS FOR BIASING SAID TRANSISTOR TO ESTABLISH A PREDETERMINED QUIESCENT CURRENT IN SAID LOAD IMPEDANCE WHEN SAID INPUT SIGNALS ARE OF SUBSTANTIALLY EQUAL VALUES.
References Cited (Backward Citations)
US3063018A
Cited
US3189811A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1969-10-03 | 1970-04-04 | 1970-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1973-10-03 | 1974-04-04 | 1974-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1977-10-03 | 1978-04-04 | 1978-10-04 | $7700.00 | Window Closed / Lapsed |