Isolated base four-layer semiconductor system

Claim 2

A GATE-CONTROLLED SWITCH WHICH COMPRISES: (A) A SEMICONDUCTOR WAGER OF A FIRST CONDUCTIVITY TYPE HAVING LAYERS OF OPPOSITE CONDUCTIVITY TYPE OF THE TOP SURFACE AND THE BOTTOM SURFACE THEREOF FORMING RECTIFYING JUNCTIONS, (B) AN EMITTER ZONE OF SAID FIRST CONDUCTIVITY TYPE IN SAID TOP SURFACE FORMING A RECTIFYING JUNCTION WITH THE LAYER ON SAID TOP SURFACE OVER A FRACTION OF SAID TOP SURFACE, (C) SAID WAFER HAVING A CHANNEL EXTENDING FROM SAID TOP SURFACE TO A DEPTH BELOW THE BOTTOM OF THE TOP SURFACE LAYER DIVIDING BOTH SAID EMITTER ZONE AND SAID TOP SURFACE LAYER INTO TWO SURFACE ZONES, (D) SEPARATE OHMIC CONNECTIONS TO EACH OF THE TWO ZONES OF SAID TOP SURFACE LAYER AND TO THE BOTTOM SURFACE LAYER, AND (E) AN OHMIC CONNECTION COMMON TO BOTH ZONES OF SAID EMITTER ZONE.

Claim 3

A GATE-CONTROLLED SWITCH CIRCUIT COMPRISING: (A) A SEMICONDUCTOR DEVICE HAVING A PNPN CONFIGURATION, SAID CONFIGURATION HAVING A P-CONDUCTIVITY EMITTER AND AN N-CONDUCTIVITY BASE, A P-CONDUCTIVITY BASE AND AN N-CONDUCTIVITY EMITTER, RESPECTIVELY, AND A CHANNEL EXTENDING THROUGH SAID N-CONDUCTIVITY EMITTER AND SAID P-CONDUCTIVITY BASE, SAID N EMITTER BEING SEPARATED INTO TWO EMITTER ZONES AND SAID P BASE BEING SEPARATED INTO TWO BASE ZONES; (B) AN OHMIC CONNECTION ON SAID P EMITTER AND SEPARATE OHMIC CONNECTIONS ON EACH OF SAID P BASE ZONES; (C) AN OHMIC CONNECTION LEADING TO BOTH OF SAID TWO EMITTER ZONES; (D) A CURRENT SOURCE CONNECTED IN A SERIES CIRCUIT WHICH INCLUDES CONNECTIONS TO SAID P EMITTER AND TO BOTH OF SAID N EMITTER ZONES; (E) BIAS MEANS CONNECTED BETWEEN ONE OF SAID P BASE ZONES AND SAID N EMITTER; AND (F) CONTROL MEANS CONNECTED BETWEEN THE SECOND OF SAID P BASE ZONES AND BOTH OF SAID N EMITTER ZONES, WHEREBY THE FUNCTION OF SAID BIAS MEANS IS TO MODIFY THE DIVISION OF CURRENT BETWEEN SAID TWO N EMITTER ZONES AND THE FUNCTION OF SAID CONTROL MEANS IS TO INITIATE AND TERMINATE CURRENT FLOW BETWEEN SAID P EMITTER AND SAID N EMITTER ZONES.

Claim 4

A GATE-CONTROLLED SWITCH CIRCUIT COMPRISING: (A) A SEMICONDUCTOR DEVICE HAVING A PNPN CONFIGURATION, SAID CONFIGURATION HAVING A P-CONDUCTIVITY EMITTER AND AN N-CONDUCTIVITY BASE, A P-CONDUCTIVITY BASE AND AN N-CONDUCTIVITY EMITTER, RESPECTIVELY, AND A CHANNEL EXTENDING THROUGH SAID N-CONDUCTIVITY EMITTER AND SAID P-CONDUCTIVITY BASE, SAID N EMITTER BEING SEPARATED INTO TWO EMITTER ZONES AND SAID P BASE BEING SEPARATED INTO TWO BASE ZONES; (B) AN OHMIC CONNECTION ON SAID P EMITTER AND SEPARATE OHMIC CONNECTIONS ON EACH OF SAID P BASE ZONES; (C) AN OHMIC CONNECTION LEADING TO BOTH OF SAID TWO EMITTER ZONES; (D) A CURRENT SOURCE CONNECTED IN A SERIES CIRCUIT WHICH INCLUDES CONNECTIONS TO SAID P EMITTER AND TO BOTH OF SAID N EMITTER ZONES; (E) BIAS MEANS CONNECTED BETWEEN ONE OF SAID P BASE ZONES AND SAID N EMITTER; AND (F) CONTROL MEANS CONNECTED BETWEEN THE SECOND OF SAID P BASE ZONES AND BOTH OF SAID N EMITTER ZONES, WHEREBY THE FUNCTION OF SAID BIAS MEANS IS TO MODIFY THE DIVISION OF CURRENT BETWEEN SAID TWO N EMITTER ZONES AND THE FUNCTION OF SAID CONTROL MEANS IS TO INITIATE AND TERMINATE CURRENT FLOW BETWEEN SAID P EMITTER AND SAID N EMITTER ZONES.