Semiconductor gating circuits for counter employing single signal source and diode matrix for effecting sequencing

Claim 1

A COUNTING CIRCUIT INCLUDING A PLURALITY OF COUNTING STAGES, EACH COMPRISING A COUNTING DEVICE HAVING INPUT AND OUTPUT ELECTRODES, ALL OF SAID DEVICES BEING INTERCONNECTED SO THAT ONLY ONE DEVICE AT A TIME CAN REGISTER A COUNT, EACH INPUT ELECTRODE BEING CONNECTED THROUGH A FIRST DIODE AND A RESISTIVE PATH TO A VOLTAGE SOURCE AND THROUGH SAID FIRST DIODE AND A SECOND DIODE TO A COMMON SIGNAL INPUT LINE, A SOURCE OF COUNTING PULSES COMPRISING A PULSE GENERATING SEMICONDUCTOR DEVICE HAVING INPUT AND OUTPUT ELECTRODES, THE OUTPUT OF SAID PULSE GENERATING SEMICONDUCTOR DEVICE BEING CONNECTED TO SAID SIGNAL INPUT LINE AND THUS THROUGH SAID FIRST AND SECOND DIODES TO THE INPUT ELECTRODE OF EACH OF SAID COUNTING DEVICES, SAID PULSE GENERATING SEMICONDUCTOR DEVICE BEING NORMALLY ON AND BEING TURNED OFF TO GENERATE AN INPUT COUNTING PULSE ON SAID SIGNAL INPUT LINE, SAID PULSE GENERATING SEMICONDUCTOR DEVICE BEING NORMALLY ON SO THAT CURRENT FLOWS FROM SAID VOLTAGE SOURCE THROUGH ALL OF SAID SECOND DIODES TO GROUND, SAID CURRENT FLOW SERVING TO BLOCK ALL OF SAID FIRST DIODES EXCEPT THE FIRST DIODE POSITIONED BETWEEN A COUNTING DEVICE WHICH IS ON AND THE NEXT ADJACENT COUNTING DEVICE WHICH IS OFF, THIS EXCEPTED FIRST DIODE