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US3270256A Expired / Lapsed US ⏱️ 0.0 years remaining

Continuously graded electrode of two metals for semiconductor devices

Assignee: International Standard Electric Corp
•
Filing: 1963-10-01
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Granted: 1966-08-30
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Expires: 1983-10-01
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Abstract

Abstract 1,023,531. Semi-conductor devices. STANDARD TELEPHONES & CABLES Ltd. Oct. 18, 1963 [Oct. 19, 1962], No. 39650/62. Addition to 1,010,111. Heading H1K. Contacts to zones of a planar diffused junction device exposed through apertures in a surface oxide layer comprise bi-metallic films extending over the layer into the apertures. The upper surface of each film consists of a solderable metal and the lower surface of a different metal which adheres well to the oxide. A typical device, a silicon transistor, Fig. 6 (not shown), is formed by successive diffusions through an oxide mask to form base and emitter zones in a high resistivity N-type layer epitaxially grown on a heavily doped N-wafer. After selectively etching to expose areas of these zones contacts are made thereto by vapour depositing aluminium over the entire surface and then etching it from the coated areas. After heating to alloy the aluminium to the silicon a layer grading from chromium or chromium-copper below to gold above, or from manganese to silver is evaporated over the entire surface as described in the parent Specification and then selectively etched to leave strips 11, 12 extending to the emitter and base contacts respectively. Alternatively the strips are obtained directly by evaporation through a mask. The graded layer can also be applied without the intermediary of aluminium if the exposed surface of the base zone is heavily doped beforehand by acceptor diffusion. The back face of the wafer may be friction alloyed to a header, or coated with a graded chromiumgold film and soldered to a header constituting the collector electrode or to a similar graded film on a glass substrate. Alternatively the collector electrode may be formed in the same way as the emitter and base electrodes on the oxide coated surface. The invention is also applicable to planar diodes and solid circuits and to germanium planar devices with silicon oxide masking layers.

Inventors

  • 👤 Mills Bernard Douglas
  • 👤 Payne Roland Francis

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 12:27
CPC Classifications
B; B23; B23K; B23K1/00; H; H01; H01B; H01B1/00; C; C03; C03C; C03C17/00; C03C17/34; C03C17/36; C03C17/40; C23; C23C; C23C14/00; C23C14/02; C23C14/027; H01R; H01R4/00; H01R4/02; H10; H10N; H10N97/00; H10P; H10P95/00; H10W; H10W20/00; H10W20/40; H10W72/00; H10W72/20; H10W72/30; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/111; H10W74/114; H10W74/15; H10W76/00; H10W76/10; H10W76/12; H10W76/161; H10W90/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/073; H10W72/07331; H10W72/07337; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/531; H10W72/5363; H10W72/551; H10W72/552; H10W72/59; H10W72/851; H10W72/853; H10W72/856; H10W72/90; H10W72/941; H10W72/944; H10W72/951; H10W72/952

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 160 words
A SEMICONDUCTOR DEVICE, COMPRISING: A DIE OF SEMICONDUCTOR MATERIAL CONTAINING A BARRIER LAYER, HAVING A REGION OF ONE CONDUCTIVITY TYPE EXTENDING TO A GIVEN SURFACE OF SAID DIE; A LAYER OF INSULATING MATERIAL ON SAID GIVEN SURFACE HAVING AN APERTURE THEREIN EXPOSING A SURFACE PORTION OF SAID REGION; AN ELECTRODE OVERLYING AND IN OHMIC CONTACT WITH SAID EXXPOSED SURFACE PORTION; AND A METALLIC FILM OVERLYING SAID INSULATING LAYER AND MAKING ELECTRICAL CONTACT TO SAID ELECTRODE, SAID FILM INCLUDING A CONTINUOUSLY GRADED LAYER OF A COMPOSITE OF TWO METALS, ONE OF SAID METALS BEING ADHESIVE TO SAID ELECTRODE AND TO SAID INSULATING LAYER, THE OTHER OF SAID METALS BEING SOFT SOLDERABLE, THE GRADING OF SAID LAYER BEING SUCH THAT THE RELATIVE PROPORTION OF SAID ADHESIVE METAL IN THE REGION OF SAID FILM ADJACENT TO SIDE ELECTRODE AND TO SAID INSULATIG LAYER IS SUBSTANTIALLY GREATER THAN SAID PROPORTION IN THE REGION OF SAID FILM FURTHEREST REMOVED FROM SAID ELECTRODE AND INSULATING LAYER.
Claim 2
Dependent Claim 160 words
A SEMICONDUCTOR DEVICE, COMPRISING: A DIE OF SEMICONDUCTOR MATERIAL CONTAINING A BARRIER LAYER, HAVING A REGION OF ONE CONDUCTIVITY TYPE EXTENDING TO A GIVEN SURFACE OF SAID DIE; A LAYER OF INSULATING MATERIAL ON SAID GIVEN SURFACE HAVING AN APERTURE THEREIN EXPOSING A SURFACE PORTION OF SAID REGION; AN ELECTRODE OVERLYING AND IN OHMIC CONTACT WITH SAID EXXPOSED SURFACE PORTION; AND A METALLIC FILM OVERLYING SAID INSULATING LAYER AND MAKING ELECTRICAL CONTACT TO SAID ELECTRODE, SAID FILM INCLUDING A CONTINUOUSLY GRADED LAYER OF A COMPOSITE OF TWO METALS, ONE OF SAID METALS BEING ADHESIVE TO SAID ELECTRODE AND TO SAID INSULATING LAYER, THE OTHER OF SAID METALS BEING SOFT SOLDERABLE, THE GRADING OF SAID LAYER BEING SUCH THAT THE RELATIVE PROPORTION OF SAID ADHESIVE METAL IN THE REGION OF SAID FILM ADJACENT TO SIDE ELECTRODE AND TO SAID INSULATIG LAYER IS SUBSTANTIALLY GREATER THAN SAID PROPORTION IN THE REGION OF SAID FILM FURTHEREST REMOVED FROM SAID ELECTRODE AND INSULATING LAYER.

References Cited (Backward Citations)

US2973466A Cited
US3199002A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1969-08-29 1970-02-28 1970-08-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1973-08-29 1974-02-28 1974-08-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1977-08-29 1978-02-28 1978-08-30 $7700.00 Window Closed / Lapsed

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