Time delay apparatus

Claim 1

A TIME DELAY APPARATUS FOR PROVIDING AN OUTPUT A PREDETERMINED TIME AFTER THE APPLICATION OF A CONTINUOUS INPUT SIGNAL THERETO FOR CONTINUOUSLY PROVIDING SAID OUTPUT SO LONG AS THE INPUT SIGNAL REMAINS COMPRISING, A PAIR OF INPUT TERMINALS FOR RECEIVING SAID INPUT SIGNAL, VOLTAGE REGULATOR MEANS CONNECTED TO SAID INPUT TERMINALS, A MEASURED PULSE OSCILLATOR CONNECTED IN CIRCUIT WITH SAID TERMINALS AND WITH SAID VOLTAGE REGULATOR, SAID OSCILLATOR BEING CONNECTED AND ARRANGED FOR OPERATING CONTINUOUSLY SO LONG AS THERE IS AN INPUT CONNECTED TO SAID INPUT TERMINALS, A FREQUENCY DIVIDER CONNECTED TO SAID VOLTAGE REGULATOR AND HAVING A CHARGING CAPACITOR THEREIN, THE CHARGE OF SAID CAPACITOR BEING CONTROLLED BY THE OUTPUT OF SAID MEASURED PULSE OSCILLATOR WHEREBY SAID CAPACITOR CHARGES IN INCREMENTS THE DURATION AND FREQUENCY OF WHICH ARE CONTROLLED BY SAID OSCILLATOR, A PULSE GENERATOR NORMALLY INOPERATIVE AND ADAPTED TO BE TRIGGERED TO OPERATIVE CONDITION WHEN THE CHARGE OF SAID CAPACITOR HAS REACHED A PREDETERMINED VALUE, AN OUTPUT CIRCUIT DRIVEN BY THE SAID PULSE GENERATOR AND BEING ADAPTED TO PROVIDE THE ABOVE MENTIONED CONTINUOUS OUTPUT, WHEREIN SAID NORMALLY INOPERATIVE GENERATOR COMPRISES A UNIJUNCTION TRANSISTOR BIASED NORMALLY TO NON-CONDUCTION AND HAVING AN EMITTER ELECTRODE CONNECTED WITH SAID FREQUENCY DIVIDER TO BE AFFECTED BY THE CHARGE ON SAID CAPACITOR IN WHICH THERE IS A BOOST CIRCUIT CONNECTED BETWEEN SAID MEASURED PULSE OSCILLATOR AND PULSE GENERATOR PROVIDING A CONTINUOUS NEGATIVE POTENTIAL PULSE TO SAID UNIJUNCTION TRANSISTOR TO REDUCE THE AMOUNT OF CURRENT REQUIRED TO RENDER SAID UNIJUNCTION TRANSISTOR CONDUCTIVE.