Analog to digital pulse rate integrator and motor driven counter therefor

Claim 1

A VOLTAGE TO PULSE FREQUENCY CONVERTER COMPRISING A DIRECT CURRENT AMPLIFIER WITH CAPACITANCE FEEDBACK TO FORM AN INTEGRATING AMPLIFIER AND HAVING TWO INPUT TERMINALS, ONE OF WHICH PROVIDES A NETWORK SUMMING JUNCTION, A VOLTAGE SENSITIVE PULSE SOURCE CONNECTED TO AN OUTPUT OF THE INTEGRATING AMPLIFIER SUCH THAT UPON THE OCCURRENCE OF A PARTICULAR VOLTAGE FROM THE AMPLIFIER THE PULSE SOURCE WILL GENERATE A PULSE OF PREDETERMINED DURATION AND AMPLITUDE, SAID PULSE SOURCE BEING COUPLED TO A FEEDBACK PATH HAVING A RESISTANCE OF PREDETERMINED SIZE TO A SUMMING JUNCTION AT THE SUMMING JUNCTION INPUT TERMINAL OF THE INTEGRATING AMPLIFIER TO RESET THE AMPLIFIER, AN ADDITIONAL AMPLIFIER FUNCTIONING AS A STABILIZING D.C. PRE-AMPLIFIER, SAID ADDITIONAL AMPLIFIER HAVING A RELATIVELY LOW RESPONSE AND HAVING FIRST AND SECOND INPUT TERMINALS, THE FIRST INPUT TERMINAL SUPPLYING A SYSTEM INPUT TERMINAL AND THE SECOND INPUT TERMINAL BEING CONNECTED TO THE NETWORK VOLTAGE INPUT TERMINAL IN SUCH A MANNER THAT SAID INPUT TERMINAL RECEIVES A VOLTAGE PROPORTIONAL TO THAT AT THE SUMMING JUNCTION, AND THE OUTPUT OF SAID ADDITIONAL AMPLIFIER BEING CONNECTED AT A SECOND INPUT TERMINAL OF THE INTEGRATING AMPLIFIER.