Transistor amplifier with bias compensation

Claim 1

A TRANSISTOR AMPLIFIER, COMPRISING: (A) A FIRST AMPLIFIER STAGE INCLUDING A FIRST TRANSISTOR OF ONE CONDUCTIVITY TYPE ARRANGED IN THE COMMON EMITTER CONFIGURATION, (B) A SECOND AMPLIFIER STAGE INCLUDING A SECOND TRANSISTOR OF SAID ONE CONDUCTIVITY TYPE ARRANGED IN THE COMMON EMITTER CONFIGURATION, THE OUTPUT OF SAID FIRST STAGE BEING DIRECT-CURRENT COUPLED TO THE INPUT OF SAID SECOND STAGE, (C) A THIRD AMPLIFIER STAGE INCLUDING A THIRD TRANSISTOR OF ON OPPOSITE CONDUCTIVITY TYPE ARRANGED IN THE COMMON EMITTER CONFIGURATION, THE OUTPUT OF SAID SECOND STAGE BEING DIRECT-CURRENT COUPLED TO THE INPUT OF SAID THIRD STAGE, (D) A SOURCE OF OPERATING POTENTIAL FOR SAID THREE STAGES, MEANS CONNECTED ONE TERMINAL OF SAID SOURCE TO THE EMITTER OF SAID FIRST AND SECOND TRANSISTORS AND TO THE COLLECTOR OF SAID THIRD TRANSISTOR, SAID MEANS INCLUDING A LOAD IMPEDANCE CONNECTED TO THE COLLECTOR OF SAID THIRD TRANSISTOR, ADDITIONAL MEANS CONNECTING THE OTHER TERMINAL OF SAID SOURCE TO THE COLLECTORS OF SAID FIRST AND SECOND TRANSISTORS VIA RESPECTIVE LOAD IMPEDANCES AND TO THE EMITTER OF SAID THIRD TRANSISTOR, (E) MEANS FOR SUPPLYING NEGATIVE DIRECT-CURRENT FEEDBACK FROM THE OUTPUT OF SAID THIRD STAGE TO THE INPUT OF SAID FIRST STAGE, SAID MEANS COMPRISING OF FEEDBACK PATH WHOSE IMPEDANCE TO FEEDBACK SIGNALS INCREASES WITH FREQUENCY.