Magnetostriction delay line frequency divider with recirculating loops

Claim 1

A DELAY LINE DIVIDER FOR GENERATING A SUB-MULTIPLE OF A CLOCK FREQUENCY COMPRISING, (A) A FIRST DELAY LINE OF FIXED LENGTH, (B) MEANS FOR APPLYING A PAIR OF INPUT PULSES TO SAID FIRST DELAY LINE IN CONSECUTIVE ORDER, (C) A FIRST ONE-BIT DELAY LINE CONNECTED TO THE OUTPUT OF SAID FIRST DELAY LINE FOR DELAYING ONE OF SAID PAIR OF PULSES WITH RESPECT TO THE OTHER, (D) A SEPARATED FEEDBACK PATH FROM THE OUTPUT OF EACH DELAY LINE TO THE INPUT OF SAID FIRST DELAY LINE FOR RECIRCULATING THE PULSES IN SAID DELAY LINES, (E) CONTROL MEANS OPERABLY CONNECTED TO EACH OF SAID FEEDBACK PATHS FOR CONTROLLING THE PASSAGE OF PULSES IN SAID FEEDBACK PATHS SO AS TO EFFECT PRECESSING OF THE PULSES IN SAID DELAY LINES, (F) GATING MEANS CONNECTED TO THE OUTPUTS OF BOTH DELAY LINES FOR ALLOWING PASSAGE OF A SIGNAL ONLY AFTER SAID INPUT PULSES HAVE RECIRCULATED A PREDETERMINED NUMBER OF TIMES, AND (G) MEANS FOR APPLYING AN INPUT CLOCK FREQUENCY TO SAID CONTROL MEANS SO AS TO SYNCHRONIZE THE OPERATION THEREOF.