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US3257568A Expired / Lapsed US ⏱️ 0.0 years remaining

Transistor circuit for controlling and rectifying the current supplied to a consumer

Assignee: Eldima AG
•
Filing: 1963-03-18
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Granted: 1966-06-21
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Expires: 1983-03-18
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Abstract

No abstract record available.

Inventors

  • 👤 Diener Rudolf

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 06:02
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/02; H02M7/04; H02M7/12; H02M7/145; H02M7/155; H02M7/1555

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 257 words
A RECTIFIER CIRCUIT COMPRISING: AN ALTERNATING CURRENT SUPPLY CIRCUIT; A TRANSFORMER HAVING A PRIMARY WINDING CONNECTED FOR ENERGIZATION BY SAID SUPPLY CIRCUIT AND A CENTER-TAPPED SECONDARY WINDING ENERGIZED FROM SAID PRIMARY WINDINGS; A PAIR OF LOAD TERMINALS; A CONDUCTOR EXTENDING FROM SAID CENTER TAP TO ONE OF SAID LOAD TERMINALS; A PAIR OF RECTIFIER ELEMENTS, EACH RECTIFIER HAVING ONE OF ITS TERMINALS EACH OF THE SAME PREDETERMINED POLARITY OF SAID ARATELY CONNECTED TO ONE OF THE END TERMINALS OF SAID SECONDARY WINDING, THE TERMINALS OF OPPOSITE POLARITY OF BOTH RECTIFIER ELEMENTS BEING CONNECTED TOGETHER FOR FULLWAVE RECTIFICATION; A FIRST TRANSISTOR HAVING EMITTER, COLLECTOR AND BASE ELECTRODES, SAID FIRST TRANSISTOR HAVING ITS EMITTER-COLLECTOR CIRCUIT CONNECTED BETWEEN SAID RECTIFIER TERMINALS OF SAID OPPOSITE POLARITY AND THE OTHER ONE OF SAID LOAD TERMINALS FOR CONTROLLING THE FLOW OF RECTIFIED CURRENT TO SAID LOAD TERMINALS; A SECOND TRANSISTOR HAVING EMITTER, COLLECTOR AND BASE ELECTRODES, SAID SECOND TRANSISTOR HAVING ITS EMITTER-COLLECTOR CIRCUIT CONNECTED BETWEEN THE ONE OF SAID LOAD TERMINALS AND THE BASE OF SAID FIRST TRANSISTOR, A FIRST RESISTOR CONNECTED BETWEN SAID CENTER TAP AND SAID BASE OF SAID FIRST TRANSISTOR; A THIRD TRANSISTOR HAVING EMITTER, COLLECTOR AND BASE ELECTRODES, SAID THIRD TRANSISTOR HAVING ITS EMITTER-COLLECTOR CIRCUIT CONNECTED BETWEEN SAID RECTIFIER TERMINALS OF SAID OPPOSITE POLARITY AND THE BASE OF SAID SECOND TRANSISTOR; A SECOND RESISTOR CONNECTED TO SAID CENTER TAP AND THE BASE OF SAID SECOND TRANSISTOR; AND AN ADJUSTABLE SOURCE OF BIASING POTENTIAL CONNECTED BETWEEN SAID RECTITIFER TERMINALS OF SAID OPPOSITE POLARITY AND THE BASE OF SAID THIRD TRANSISTOR.
Claim 2
Dependent Claim 257 words
A RECTIFIER CIRCUIT COMPRISING: AN ALTERNATING CURRENT SUPPLY CIRCUIT; A TRANSFORMER HAVING A PRIMARY WINDING CONNECTED FOR ENERGIZATION BY SAID SUPPLY CIRCUIT AND A CENTER-TAPPED SECONDARY WINDING ENERGIZED FROM SAID PRIMARY WINDINGS; A PAIR OF LOAD TERMINALS; A CONDUCTOR EXTENDING FROM SAID CENTER TAP TO ONE OF SAID LOAD TERMINALS; A PAIR OF RECTIFIER ELEMENTS, EACH RECTIFIER HAVING ONE OF ITS TERMINALS EACH OF THE SAME PREDETERMINED POLARITY OF SAID ARATELY CONNECTED TO ONE OF THE END TERMINALS OF SAID SECONDARY WINDING, THE TERMINALS OF OPPOSITE POLARITY OF BOTH RECTIFIER ELEMENTS BEING CONNECTED TOGETHER FOR FULLWAVE RECTIFICATION; A FIRST TRANSISTOR HAVING EMITTER, COLLECTOR AND BASE ELECTRODES, SAID FIRST TRANSISTOR HAVING ITS EMITTER-COLLECTOR CIRCUIT CONNECTED BETWEEN SAID RECTIFIER TERMINALS OF SAID OPPOSITE POLARITY AND THE OTHER ONE OF SAID LOAD TERMINALS FOR CONTROLLING THE FLOW OF RECTIFIED CURRENT TO SAID LOAD TERMINALS; A SECOND TRANSISTOR HAVING EMITTER, COLLECTOR AND BASE ELECTRODES, SAID SECOND TRANSISTOR HAVING ITS EMITTER-COLLECTOR CIRCUIT CONNECTED BETWEEN THE ONE OF SAID LOAD TERMINALS AND THE BASE OF SAID FIRST TRANSISTOR, A FIRST RESISTOR CONNECTED BETWEN SAID CENTER TAP AND SAID BASE OF SAID FIRST TRANSISTOR; A THIRD TRANSISTOR HAVING EMITTER, COLLECTOR AND BASE ELECTRODES, SAID THIRD TRANSISTOR HAVING ITS EMITTER-COLLECTOR CIRCUIT CONNECTED BETWEEN SAID RECTIFIER TERMINALS OF SAID OPPOSITE POLARITY AND THE BASE OF SAID SECOND TRANSISTOR; A SECOND RESISTOR CONNECTED TO SAID CENTER TAP AND THE BASE OF SAID SECOND TRANSISTOR; AND AN ADJUSTABLE SOURCE OF BIASING POTENTIAL CONNECTED BETWEEN SAID RECTITIFER TERMINALS OF SAID OPPOSITE POLARITY AND THE BASE OF SAID THIRD TRANSISTOR.

References Cited (Backward Citations)

US3124698A Cited
US3068392A Cited
US3156860A Cited
US3102225A Cited
US3098192A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1969-06-20 1969-12-20 1970-06-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1973-06-20 1973-12-20 1974-06-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1977-06-20 1977-12-20 1978-06-21 $7700.00 Window Closed / Lapsed

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