Electrical neuron circuits

Claim 2

A NEURON CIRCUIT WHICH COMPRISES INPUT MEANS FOR SUMMING A PLURALITY OF EXCITATORY AND INHIBITORY INPOUT SIGNALS OF OPPOSITE POLARITY, AND CIRCUIT MEANS COUPLED TO SAID INPUT MEANS FOR RESPONDING TO THE SUM OF SAID EXCITATORY AND INHIBITORY SIGNALS OCCURRING DURING A GIVEN PERIOD OF TIME, WHEN SAID SUM EXCEEDS A CERTAIN THRESHOLD, TO PROVIDE A PLURALITY OF OUTPUT PULSES TO OPPOSITE POLARITY AND HAVING A RATE DEPENDING UPON THE DIFFERENCE BETWEEN SAID SUM AND SAID THRESHOLD, SAID RTE INCREASING NONLINEARLY WITH SAID DIFFERENCE AND SATURATING AT A MAXIMUM RATE.

Claim 3

A PULSE GENERATOR COMPRISING IN COMBINATION FIRST AND SECOND COMPLEMENTARY TRANSISTORS, EACH HAVING A BASE, AN EMITTER AND A COLLECTOR, MEANS FOR SERIALLY CONNECTING SAID TRANSISTORS BY COUPLING THE EMITTERS OF SAID TRANSISTORS TOGETHER, MEANS FOR APPLYING A FIRST ENERGIZING SIGNAL OF ONE POLARITY TO THE COLLECTOR OF SAID FIRST TRANSISTOR AND A SECOND ENERGIZING SIGNAL OF THE OPPOSITE POLARITY TO THE COLLECTOR OF SAID SECOND TRANSISTOR, SAID FIRST AND SECOND ENERGIZING SIGNALS HAVING AMPLITUDES OF SUBSTANTIALLY THE SAME ABSOLUTE MAGNITUDES, FIRST AND SECOND MEANS COUPLED TO THE BASES OF SAID FIRST AND SECOND TRANSISTORS, RESPECTIVELY, FOR BIASING SAID TRANSISTORS TO CONDUCT IN SATURATION, FIRST AND SECOND OUTPUT TERMINALS COUPLED TO THE COLLECTORS OF SAID FIRST AND SECOND TRANSISTORS, RESPECTIVELY, SAID OUTPUT TERMINALS EXHIBITING SUBSTANTIALLY ZERO POTENTIAL WHEN SAID FIRST AND SECOND TRANSISTORS ARE SATURATED, AND MEANS FOR APPLYING A REVERSE BIASING PULSE TO THE BASE OF ONE OF SAID TRANSISTORS TO CUT OFF BOTH OF SAID SERIALLY CONNECTED TRANSISTORS DURING THE DURATION OF SAID PULSE WHEREBY SAID FIRST AND SECOND OUTPUT TERMINALS PROVIDE SUBSTANTIALLY EQUAL BUT OPPOSITE OUTPUT PULSES HAVING MAGNITUDES SUBSTANTIALLY EQUAL TO THE MAGNITUDE OF SAID FIRST AND SECOND ENERGIZING SIGNALS.

Claim 4

A PULSE GENERATOR COMPRISING IN COMBINATION FIRST AND SECOND COMPLEMENTARY TRANSISTORS, EACH HAVING A BASE, AN EMITTER AND A COLLECTOR, MEANS FOR SERIALLY CONNECTING SAID TRANSISTORS BY COUPLING THE EMITTERS OF SAID TRANSISTORS TOGETHER, MEANS FOR APPLYING A FIRST ENERGIZING SIGNAL OF ONE POLARITY TO THE COLLECTOR OF SAID FIRST TRANSISTOR AND A SECOND ENERGIZING SIGNAL OF THE OPPOSITE POLARITY TO THE COLLECTOR OF SAID SECOND TRANSISTOR, SAID FIRST AND SECOND ENERGIZING SIGNALS HAVING AMPLITUDES OF SUBSTANTIALLY THE SAME ABSOLUTE MAGNITUDES, FIRST AND SECOND MEANS COUPLED TO THE BASES OF SAID FIRST AND SECOND TRANSISTORS, RESPECTIVELY, FOR BIASING SAID TRANSISTORS TO CONDUCT IN SATURATION, FIRST AND SECOND OUTPUT TERMINALS COUPLED TO THE COLLECTORS OF SAID FIRST AND SECOND TRANSISTORS, RESPECTIVELY, SAID OUTPUT TERMINALS EXHIBITING SUBSTANTIALLY ZERO POTENTIAL WHEN SAID FIRST AND SECOND TRANSISTORS ARE SATURATED, AND MEANS FOR APPLYING A REVERSE BIASING PULSE TO THE BASE OF ONE OF SAID TRANSISTORS TO CUT OFF BOTH OF SAID SERIALLY CONNECTED TRANSISTORS DURING THE DURATION OF SAID PULSE WHEREBY SAID FIRST AND SECOND OUTPUT TERMINALS PROVIDE SUBSTANTIALLY EQUAL BUT OPPOSITE OUTPUT PULSES HAVING MAGNITUDES SUBSTANTIALLY EQUAL TO THE MAGNITUDE OF SAID FIRST AND SECOND ENERGIZING SIGNALS.

Claim 5

A NEURON CIRCUIT RESPONSIVE TO A PLURALITY OF INPUT SIGNALS, COMPRISING IN COMBINATION, A SUMMING CIRCUIT FOR DERIVING THE SUM OF SAID INPUT SIGNALS, AN INTEGRATING CIRCUIT HAVING A PREDETERMINED TIME CONSTANT FOR INTEGRATING SAID SUM SIGNALS TO PROVIDE AN INTEGRATED SIGNAL, ISOLATING MEANS FOR COUPLING SAID INTEGRATING CIRCUIT TO SAID SUMMING CIRCUIT TO MAINTAIN SAID TIME CONSTANT SUBSTANTIALLY INVARIABLE, A THRESHOLD CIRCUIT COUPLED TO SAID INTEGRATING CIRCUIT AND HAVING A NORMALLY INACTIVE STATE AND CONDITIONABLE TO AN ACTIVE STATE WHEN SAID INTEGRATED SIGNAL EXCEEDS A CERTAIN THRESHOLD LEVEL, A PULSE GENERATING CIRCUIT COUPLED TO SAID THRESHOLD CIRCUIT FOR PROVIDING OUTPUT PULSES WHEN SAID THRESHOLD CIRCUIT IS CONDITIONED INTO ITS ACTIVE STATE BY SAID INTEGRATED SIGNAL, AND A REFRACTORY CIRCUIT FOR FEEDING BACK SAID OUTPUT PULSES SAID PULSE GENERATING CIRCUIT INTO SAID INTEGRATING CIRCUIT.

Claim 6

A NEURON CIRCUIT RESPONSIVE TO A PLURALITY OF INPUT SIGNALS, COMPRISING IN COMBINATION, A SUMMING CIRCUIT FOR DERIVING THE SUM OF SAID INPUT SIGNALS, AN INTEGRATING CIRCUIT HAVING A PREDETERMINED TIME CONSTANT FOR INTEGRATING SAID SUM SIGNALS TO PROVIDE AN INTEGRATED SIGNAL, ISOLATING MEANS FOR COUPLING SAID INTEGRATING CIRCUIT TO SAID SUMMING CIRCUIT TO MAINTAIN SAID TIME CONSTANT SUBSTANTIALLY INVARIABLE, A THRESHOLD CIRCUIT COUPLED TO SAID INTEGRATING CIRCUIT AND HAVING A NORMALLY INACTIVE STATE AND CONDITIONABLE TO AN ACTIVE STATE WHEN SAID INTEGRATED SIGNAL EXCEEDS A CERTAIN THRESHOLD LEVEL, A PULSE GENERATING CIRCUIT COUPLED TO SAID THRESHOLD CIRCUIT FOR PROVIDING OUTPUT PULSES WHEN SAID THRESHOLD CIRCUIT IS CONDITIONED INTO ITS ACTIVE STATE BY SAID INTEGRATED SIGNAL, AND A REFRACTORY CIRCUIT FOR FEEDING BACK SAID OUTPUT PULSES SAID PULSE GENERATING CIRCUIT INTO SAID INTEGRATING CIRCUIT.