Computer clock phase lock

Claim 1

IN A DATA PROCESSING SYSTEM OF THE TYPE WITHIN WHICH VARIOUS MEANS MAY SENSE ERRORS OR FAILURES IN SAID SYSTEM, AND THERE IS PROVIDED MEANS FOR GENERATING FAULT SIGNALS IN RESPONSE TO CERTAIN ERRORS OR FAILURES, SAID SYSTEM BEING RESETTABLE INTO A RUNNING CONDITION BY A SYSTEM RESETTING SIGNAL, A TIMING CONTROL COMPRISING: A SOURCE OF ALTERNATING BASIC TIMING SIGNAL; A STOP CIRCUIT SETTABLE INTO EITHER ONE OF TWO STABLE STATES, SAID STOP CIRCUIT WHEN SET INTO A FIRST ONE OF SAID STATES GENERATING A STOP SIGNAL; CLOCK CONTROL MEANS RESPONSIVE TO SAID SOURCE AND TO SAID STOP SIGNAL FOR GENERATING ALTERNATING BASIC TIMING SIGNALS IN RESPONSE TO THE ABSENCE OF SAID STOP SIGNAL AND FOR GENERATING A STEADY SIGNAL IN RESPONSE TO SAID STOP SIGNAL; TIMING SIGNAL GENERATING MEANS RESPONSIVE TO SAID CLOCK CONTROL MEANS FOR GENERATING TIMING SIGNALS FOR SAID SYSTEM; MEANS RESPONSIVE TO SAID FAULT SIGNALS FOR SETTING SAID STOP MEANS IN SAID FIRST STATE; AND MEANS RESPONSIVE TO SAID SYSTEM RESETTING SIGNALS AND TO SAID SOURCE FOR RESETTING SAID STOP CIRCUIT INTO SAID SECOND CONDITION IN RESPONSE TO A SIGNAL FROM SAID SOURCE WHICH IS EQUAL TO THE OUTPUT FROM SAID CLOCK CONTROL MEANS AT THE TIME THAT SAID STOP CIRCUIT IS RESET INTO SAID SECOND CONDITION.