Pulse delay circuits

Claim 1

A DELAY CIRCUIT COMPRISING THE COMBINATION OF AN INTEGRATING CIRCUIT INCLUDING THE STEPS COMBINATION OF A RESISTIVE ELEMENT AND A REACTIVE STORAGE ELEMENT, A FIRST TRANSISTOR OF ONE CONDUCTIVITY TYPE HAVING INPUT AND COMMON ELECTRODES COUPLED ACROSS SAID REACTIVE STORAGE ELEMENT, AND AN OUTPUT ELECTRODE, BIASING MEANS CONNECTED ACROSS SAID INTEGRATING CIRCUIT TO CHARGE SAID REACTIVE STORAGE ELEMENT IN ONE DIRECTION TO QUIESCENTLY BIAS SAID FIRST TRANSISTOR TO CUT OFF, MEANS FOR APPLYING AN INPUT PULSE TO SAID INTEGRATING CIRCUIT OF A POLARITY TO CHARGE SAID REACTIVE STORAGE ELEMENT IN A DIRECTION OPPOSITE TO SAID ONE DIRECTION SO AS TO TURN ON SAID FIRST TRANSISTOR AFTER A PREDETERMINED TIME DELAY, A SECOND TRANSISTOR OF OPPOSITE CONDUCTIVITY TYPE TO SAID FIRST TRANSISTOR COUPLED TO SAID INTEGRATING CIRCUIT IN A MANNER TO DISCHARGE SAID REACTIVE STORAGE ELEMENT AND TURN OFF SAID FIRST TRANSISTOR AT THE TERMINATION OF SAID INPUT PULSE, AND MEANS COUPLED TO THE OUTPUT ELECTRODE OF SAID FIRST TRANSISTOR FOR DERIVING AN OUTPUT PULSE HAVING A LEADING EDGE DELAYED SAID PREDETERMINED TIME WITH RESPECT TO THE LEADING EDGE OF SAID INPUT PULSE BUT A TRAILING EDGE SUBSTANTIALLY COINCIDING WITH THE TRAILING EDGE OF SAID INPUT PULSE.