Inhibit logic circuit

Claim 1

IN APPARATUS FOR PERFORMING LOGICAL OPERATIONS AND INCLUDING AT LEAST ONE BISTABLE MAGNETIC CORE COERCIBLE FROM EITHER OF ITS STATES TO THE OTHER AND HAVING A POWER WINDING, AT LEAST ONE INHIBITING WINDING AND AN OUTPUT WINDING COUPLED THERETO, SAID APPARATUS ALSO INCLUDING MEANS FOR APPLYING A POWER SIGNAL TO SAID POWER WINDING FOR SWITCHING SAID CORE UNLESS INHIBITED BY AN INHIBITING SIGNAL APPLIED TO SAID INHIBITTING WINDING, THE IMPROVEMENT COMPRISING TRANSISTOR CIRCUIT MEANS RESPONSIVE TO OUTPUT SIGNALS INDUCED IN SAID OUTPUT WINDING FOR PROVIDING AN INHIBITING SIGNAL FOR APPLICATION TO SAID INHIBITING WINDING, SAID TRANSISTOR CIRCUIT MEANS COMPRISING: FIRST AND SECOND TRANSISTORS EACH COMPRISING A BASE, AN EMITTER AND A COLLECTOR, MEANS COUPLING SAID OUTPUT WINDING TO THE BASE OF SAID FIRST TRANSISTOR, MEANS COUPLING THE COLLECTOR OF SAID FIRST TRANSISTOR TO THE BASE OF SAID SECOND TRANSISTOR AND THE COLLECTOR OF SAID SECOND TRANSISTOR TO THE BASE OF SAID FIRST TRANSISTOR SO AS TO PROVIDE FOR BISTABLE OPERATION OF SAID CIRCUIT MEANS IN RESPONSE TO THE SIGNAL INDUCED IN SAID OUTPUT WINDING AS A RESULT OF THE SWITCHING OF SAID CORE, A LOAD IMPEDANCE MEANS, A DIODE COUPLED TO THE COLLECTOR OF ONE OF SAID TRANSISTORS, AND MEANS COUPLING SAID INHIBITING WINDING BETWEEN SAID LOAD IMPEDANCE MEANS AND SAID DIODE, SAID DIODE BEING POLED IN THE DIRECTION OF INHIBIT CURRENT FLOW.