Electrical timing circuit

Claim 1

AN ELECTRICAL TIMING CIRCUIT FOR INITIATING AN OUTPUT LOAD INTO OPERATION AFTER THE LAPSE OF A PRESELECTED INTERVAL COMPRISING A RESISTOR AND A CAPACITOR CONNECTED AS A SERIES CIRCUIT, A FIRST CONNECTION POINT IN SAID SERIES CIRCUIT BETWEEN SAID RESISTOR AND SAID CAPACITOR, MEANS FOR APPLYING A VOLTAGE ACROSS SAID SERIES CIRCUIT TO DEVELOP AT SAID FIRST CONNECTION POINT A POTENTIAL WHICH VARIES IN TIME IN RELATION TO THE TIME CONSTANT OF SAID SERIES CIRCUIT, A FIRST VOLTAGE DIVIDER NETWORK CONNECT ACROSS SAID VOLTAGE MEANS AND SAID SERIES CIRCUIT, A SECOND CONNECTION POINT IN SAID FIRST VOLTAGE DIVIDER NETWORK FOR TAPPING A PRESELECTED CONSTANT POTENTIAL THEREFROM, A SWITCHING AMPLIFIER INCLUDING AT LEAST FIRST AND SECOND TRANSISTORS EACH HAVING BASE, EMITTER AND COLLECTOR ELECTRODES, A RECTIFIER ELEMENT CONNECTED BETWEEN SAID FIRST CONNECTION POINT AND SAID BASE ELECTRODE OF SAID FIRST TRANSISTOR SO THAT SAID RECTIFIER ELEMENT IS REVERSE BIASED BY THE INITIAL VOLTAGE DIFFERENCE ACROSS SAID FIRST AND SECOND CONNECTION POINTS AND FORWARD BIASED BY THAT VOLTAGE DIFFERENCE AFTER THE LAPSE OF SAID PRESELECTED TIME INTERVAL, SAID TRANSISTORS BEING CONSTRUCTED AND ARRANGED FOR PROVIDING CASCADE AMPLIFICATION A SECOND VOLTAGE DIVIDER NETWORK CONNECTED BETWEEN SAID FIRST AND SECOND CONNECTION POINTS, SECOND CIRCUIT MEANS COUPLING A BIAS VOLTAGE FROM SAID SECOND VOLTAGE DIVIDER NETWORK FOR REVERSE BIASING AT LEAST ONE OF SAID TRANSISTORS, AND AN OUTPUT CIRCUIT FOR SAID AMPLIFIER INCLUDING SAID OUTPUT LOAD, SID AMPLIFIER BEING REVERSE BIASED BY TE INITIAL VOLTAGE DIFFERENCE ACROSS SAID FIRST AND SECOND CONNECTION POINTS AND BEING FORWARD BIASED BY SAID VOLTAGE DIFFERENCE AFTER SAID PRESELECTED TIME INTERVAL DETERMINED BY THE TIME CONSTANT OF SAID SERIES CIRCUIT, WHEREBY SAID SWITCHING AMPLIFIER PRODUCES AN OUTPUT CURRENT FOR THE OPERATION OF SAID OUTPUT LOAD AFTER LAPSE OF SAID PRESELECTED TIME INTERVAL.