Free running multivibrator transistor circuit

Claim 1

A FREE RUNNING MULTI-VIBRATOR DEVICE COMPRISING (A) FIRST AND SECOND TRANSISTORS, (B) FIRST AND SECOND COUPLING ARMS INTERCONNECTING SAID TRANSISTORS FOR MUTUAL REVERSAL OF STATE, (C) FIRST COUPLING ARM INCLUDING (1) A FIRST CAPACITANCE, (2) MEANS COUPLING ONE SIDE OF SAID FIRST CAPACITANCE TO THE BASE OF SAID FIRST TRANSISTOR, (3) MEANS COUPLING THE OTHER SIDE OF SAID FIRST CAPACITANCE TO THE COLLECTOR OF SAID SECOND TRANSANCE PATH FOR COLLECTOR CURRENT OF SAID SECOND TRANSISTOR BETWEEN THE COLLECTOR OF D SECOND TRANSISTOR BETWEEN THE COLLECTOR OF SAID SECOND TRANSISTOR AND SAID FIRST CAPACITANCE, (D) SAID SECOND CAPACITANCE, (1) SECOND CAPACITANCE, (2) MEANS COUPLING ONE SIDE OF SAID SECOND CAPACITANCE TO THE BASE OF SAID SECOND TRANSISTOR, (3) MEANS COUPLING THE OTHER SIDE OF SAID SECOND CAPACITANCE TO THE COLLECTOR OF SAID FIRST TRANSISTOR AND PROVIDING A SUBSTANTIALLY ZERO IMPEDANCE PATH FOR COLLECTOR CURRENT OF SAID FIRST TRANSISTOR BETWEEN THE COLLECTOR OF SAID FIRST RRANSISTOR AND SAID SECOND CAPACITANCE, (E) RESISTANCE MEANS CONNECTED IN SERIES WITH SAID FIRST CAPACITANCE TO FORM, WITH SAID FIRST CAPACITANCE, A FIRST TIMING CIRCUIT, AND MEANS FOR CONNECTING SAID FIRST TIMING CIRCUIT ACROSS A SOURCE OF POTENTIAL TO CHARGE SAID FIRST CAPACITANCE, (F) FURTHER RESISTANCE MEANS CONNECTED IN SERIES WITH SAID SECOND CAPACITANCE TO FORM, WITH SAID SECOND CAPACITANCE, A SECOND TIMING CIRCUIT, AND MEANS FOR CONNECTING SAID SECOND TIMING CIRCUIT ACROSS SAID SOURCE OF POTENTIAL TO CHARGE SAID SECOND CAPACITANCE, (G) FIRST DIODE MEANS CONNECTED BETWEEN SAID ONE SIDER OF SAID FIRST CAPACITANCE AND THE EMITTER OF SAID FIRST TRANSISTOR, SAID FIRST DIODE MEANS BEING POLED TO CONDUCT COLLECTOR CURRENT OF SAID SECOND TRANSISTOR FLOWING THROUGH SAID FIRST CAPACITANCE, (H) SECOND DIODE MEANS CONNECTED BETWEEN SAID ONE SIDE OF SAID SECOND CAPACITANCE AND THE EMITTER OF SAID SECOND TRANSISTOR, SAID SECOND DIODE MEANS BEING POLED TO CONDUIT COLLECTOR CURRENT OF SAID FIRST TRANSISTOR FLOWING THROUGH SAID SECOND CAPACITANCE, (I) A LOW IMPEDANCE MEANS CONNECTING TOGETHER THE EMITTERS OF SAID TRANSISTORS; WHEREBY, WHEN SAID FIRST TRANSISTOR CONDUCTS, SAID FIRST CAPACITANCE CHARGES THROUGH SAID FIRST TIMING CIRCUIT UNTIL SAID ONE SIDE OF SAID FIRST CAPACITANCE APPROACHES THE EMITTER POTENTIAL OF SAID FRIST TRANSISTOR TO TERMINATE CONDUCTION OF SAID FIRST TRANSISTOR, SAID SECOND TRANSISTOR THEN COMMENCING CONDUCTION AND SAID FIRST CAPACITANCE DISCHARGING THROUGH A VERY LOW IMPEDANCE PATH CONSISTING OF THE EMITTER-COLLECTOR PATH OF SAID SECOND TRANSISTOR, SAID MEANS (C) (3), SAID FIRST CAPACITANCE, SAIF FIRST DIODE MEANS, AND SAID LOW IMPEDANCE MEANS (I), FOR RAPID RECOVERY OF SAID FIRST CAPACITANCE, AND AS SAID SECOND TRANSISTOR CONDUCTS, SAID SECOND CAPACITANCE CHARGES THROUGH SAID SECOND TIMING CIRCUIT UNTIL SAID ONE SIDE OF SAID SECOND CAPACITANCE APPROACHES THE EMITTER POTENTIAL OF SAID SECOND TRANSISTOR TO TERMINATE CONDUCTION OF SAID SECOND TRANSISTOR, SAID FIRST TRANSISTOR THEN COMMENCING CONDUCTION AND SAID SECOND CAPACITANCE DISCHARGING THROUGH A VERY LOW IMPEDANCE PATH CONSISTING OF THE EMITTER-COLLECTOR PATH OF SAID FIRST TRANSISTOR, SAID MEANS (D) (3), SAID SECOND CAPACITANCE, SAID SECOND DIODE MEANS, AND SAID LOW IMPEDANCE MEANS (I), FOR RAPID RECOVERY OF SAID SECOND CAPACITANCE.