Dividing computer

Claim 1

IN A MEMORY-CENTERED COMPUTER HAVING MEANS FOR STORING A DIVISOR AND A DIVIDEND REMAINDER; (A) AN ADDRESSABLE MEMORY HAVING AN ADD TABLE OF SUMS LOCATABLE BY AN ADDRESS INCLUDING THE DIGITS TO BE ADDED; (B) AN ADDRESS REGISTER FOR ACCESSING LOCATIONS IN SAID MEMORY; (C) QUOTIENT DIGIT ADDRESS DEVELOPING MEANS FOR INCREMENTING BY 1 THE VALVE IN SAID ADDRESS REGISTER; (D) SUBTRACT PROGRAM MEANS TO SUBTRACT THE DIVISOR FROM THE DIVIDEND REMAINDER; (E) SUBTRACT COMPLETE DECISION MEANS ASSOCIATED WITH SAID SUBTRACT PROGRAM MEANS TO SIGNAL COMPLETION OF THE SUBTRACTION OF DIVISOR FROM DIVIDEND REMAINDER; (F) REMAINDER MINUS DECISION MEANS ASSOCIATED WITH SAID SUBTRACT COMPLETE DECISION MEANS FOR PRODUCING REMAINDER NEGATIVE AND REMAINDER POSITIVE SIGNALS; (G) MEANS RESPONSIVE TO A POSITIVE SIGNAL FROM SAID REMAINDER MINUS DECISION MEANS TO ENERGIZE SAID QUOTIENT DIGIT ADDRESS DEVELOPING MEANS TO INCREMENT THE SETTING OF SAID ADDRESS REGISTER; AND (H) QUOTIENT DIGIT DEVELOPMENT MEANS RESPONSIVE TO SAID REMAINDER NEGATIVE SIGNAL FROM SAID REMAINDER MINUS DECISION MEANS AND TO THE CURRENT SETTING OF SAID ADDRESS REGISTER TO READOUT FROM SAID ADD TABLE THE QUOTIENT DIGIT.