Electronic clamping circuit

Claim 1

VOLTAGE CLAMPING CIRCUIT HAVING A GOOD LOW FREQUENCY RESPONSE COMPRISING AN INPUT TERMINAL, OUTPUT TERMINAL, A CAPACITOR FOR COUPLING SAID INPUT TERMINAL WITH SAID OUTPUT TERMINAL, A REFERENCE VOLTAGE SOURCE, A DIODE CONNECTED BETWEEN SAID OUTPUT TERMINAL SIDE OF SAID CAPACITOR AND SAID REFERENCE VOLTAGE, SAID DIODE BEING ORIENTED TO BE REVERSELY BIASED BY AN INPUT VOLTAGE WAVEFORM BEING APPLIED TO SAID INPUT TERMINAL WHEN THAT VOLTAGE DECREASES FROM ITS CLAMPED VOLTAGE LEVEL, A CONTINUOUSLY CONDUCTING TRANSISTOR MEANS CONNECTED IN AN EMITTER FOLLOWER CONFIGURATION, THE BASE OF SAID TRANSISTOR MEANS BEING CONNECTED TO SAID OUTPUT TERMINAL, THE BASE EMITTER CIRCUIT OF SAID TRANSISTOR MEANS ACTING AS A SOURCE OF A SMALL CONDUCTING CURRENT FOR SAID DIODE WHENEVER THE VOLTAGE OUTPUT WAVEFORM AT SAID OUTPUT TERMINAL IS AT ITS CLAMPED VOLTAGE LEVEL AND PROVIDING A HIGH REFLECTED IMPEDANCE TO SAID CAPACITOR WITHOUT REGARD TO THE MAGNITUDE OF THE VOLTAGE LEVEL AT SAID OUTPUT TERMINAL.