Information processing circuit

Claim 1

IN COMBINATION IN A SAMPLE AND HOLD CIRCUIT, SUBSTANTIALLY NONREFLECTING DELAY LINE MEANS INCLUDING N TAPS AND A TERMINATING IMPEDANCE AT ONE END THEREOF TO MIMIMIZE SIGNAL REFLECTIONS, MEANS FOR APPLYING A CONTINUOUSLY VARIABLE ANALOG INPUT SIGNAL TO THE OTHER END OF SAID DELAY LINE MEANS, SAID N TAPS BEING SO POSITIONED ALONG SAID DELAY LINE MEANS THAT THE TIME REQUIRED FOR THE INPUT SIGNAL TO PROPAGATE BETWEEN ADJACENT TAPS IS T SECONDS, N GATE MEANS RESPECTIVELY CONNECTED TO SAID TAPS, EACH OF SAID GATE MEANS INCLUDING AN OUTPUT TERMINAL, AND MEANS DISTINCT FROM SAID DELAY LINE MEANS FOR ENABLING SAID N GATE MEANS IN SEQUENCE BY RESPECTIVELY SUPPLYING THERETO N ENABLING SIGNALS WHOSE PERIOD IS T SECONDS, WHEREBY A PARTICULAR SELECTED PORTION OF THE APPLIED ANALOG INPUT SIGNAL APPEARS IN SEQUENCE AT THE SUCCESSIVE TAPS OF SAID DELAY LINE MEANS AND ALSO APPEARS AT THE RESPECTIVE OUTPUT TERMINALS OF SAID N GAGE MEANS IN TIME COINCIDENCE WITH THE OCCURRENCE OF SAID ENABLING SIGNALS.