Segmented arithmetic device

Claim 1

IN A PARALLEL BINARY ADDER: FIRST AND SECOND OPERAND STORAGE REGISTERS MADE UP OF A MULTIPLICITY OF PARALLEL STATIC FLIP-FLOP CIRCUITS, EACH FLIP-FLOP CAPABLE OF SELECTIVELY STORING A SIGNAL REPRESENTING A DIGIT VALUE OF "O" WHEN CLEARED AND A VALUE OF "1" WHEN SET, SAID FIRST OPERAND STORAGE REGISTER SELECTIVELY PROVIDING AN OUTPUT SIGNAL GROUPING INDICATIVE OF A SINGLE AUGEND OR OF PARALLEL INDEPENDENT MULTIPLE AUGENDS, SAID SECOND OPERAND STORAGE REGISTER SELECTIVELY PROVIDING AN OUTPUT SIGNAL GROUPING INDICATIVE OF A SINGLE ADDEND OR OF PARALLEL MULTIPLE INDEPENDENT ADDENDS; A PLURALITY OF FIRST ARITHMETIC CIRCUITS RESPONSIVE TO SIGNALS RECEIVED FROM RESPECTIVE STAGES OF SAID FIRST AND SECOND OPERAND STORAGE REGISTERS, WHERE SAID ARITHMETIC CIRCUITS PERFORM A BIT-BY-BIT INVERTED EXCLUSIVE-OR LOGICAL FUNCTION, THEREBY PROVIDING TWO GROUPINGS OF RESULTANT SIGNALS, THE FIRST RESULTANT GROUPING BEING A PARTIAL-RESULTANT REPRESENTING THE INVERTED BIT-DIFFERENCES OF THE RESPECTIVE STAGES OF THE TWO OPERAND STORAGE REGISTERS AND THE SECOND RESULTANT GROUPING OF SIGNALS INDICATES THE BIT-BY-BIT CONDITION WHERE INTER-DIGIT BORROW SIGNALS ARE GENERATED; A FIRST AUXILIARY REGISTER COUPLED TO SAID PLURALITY OF FIRST ARITHMETIC CIRCUITS, FOR STORING THE INVERTED BITDIFFERENCE SIGNALS IN ORDER GROUPS OF ADJACENT ORDERED DIGIT POSITIONS; A SECOND AUXILIARY REGISTER COUPLED TO SAID PLURALITY OF FIRST ARITHMETIC CIRCUITS FOR STORING THE INTER-DIGIT BORROW SIGNALS IN ORDERED GROUPS OF ADJACENT ORDERED DIGIT POSITIONS; A PLURALITY OF GROUP-BORROW ENABLING CIRCUITS RESPONSIVE TO SIGNALS FROM PREDETERMINED GROUPS OF ADJACENT DIGIT POSITIONS OF SAID FIRST AUXILIARY REGISTER, THE ENABLING CIRCUITS PROVIDING OUTPUT SIGNALS INDICATIVE OF THE PRESENCE OF SIGNALS HELD WITHIN SAID GROUPINGS OF ADJACENT DIGIT POSITIONS, WHICH COULD SATISFY BORROW SIGNALS PROPAGATED FROM LOWER-ORDERED GROUPINGS OF ADJACENT DIGIT POSITIONS OF SAID SECOND AUXILIARY REGISTER; A PLURALITY OF GROUP-BORROW SIGNAL PROPAGATING CIRCUITS RESPONSIVE TO SIGNALS FROM SAID PREDETERMINED SIGNAL GROUPINGS OF ADJACENT DIGIT POSITIONS OF SAID FIRST AUXILIARY REGISTER AND RESPONSIVE TO SIGNALS FROM CORRESPONDING GROUPS OF SAID PREDETERMINED SIGNAL GROUPINGS OF ADJACENT DIGIT POSITIONS OF SAID SECOND AUXILIARY REGISTER, WHEREBY GROUP-BORROW SIGNALS ARE PROPAGATED FROM GROUPS WHEREIN THE HIGHEST ORDERED INTER-DIGIT BORROW CANNOT BE SATISFIED WITHIN THE PREDETERMINED SIGNAL GROUPING OF ADJACENT DIGIT POSITIONS OF SAID FIRST AUXILIARY REGISTER, SUCH GROUPBORROW SIGNAL PROPAGATION BEING FROM LOWER-ORDERED GROUPS OF INTER-DIGIT BORROW SIGNALS TO HIGHER-ORDERED GROUPS OF INVERTED BIT-DIFFERENCE SIGNALS; SEGMENT-SIZE SIGNAL MEANS; A PLURALITY OF SEGMENT-SIZE SELECTION CIRCUITS RESPONSIVE TO SAID GROUP-BORROW ENABLING SIGNALS AND TO SAID GROUP-BORROW SIGNALS IN CONJUNCTION WITH SAID SEGMENT-SIZE SIGNALS TO PROVIDE INTRINSIC SIGNALS SUCH THAT THE APPROPRIATE END-AROUND BORROW SIGNAL PATHS ARE SELECTED; A PLURALITY OF DIGIT-BORROW SIGNAL PROPAGATION CIRCUITS RESPONSIVE TO SAID INTRINSIC SIGNALS AND TO SAID INTERDIGIT BORROW SIGNALS STORED IN SAID SECOND AUXILIARY REGISTER TO PROVIDE THE FINAL BORROW SIGNAL PATTERN SUCH THAT WHEN COMBINED WITH THE INVERTED BITDIFFERENCE SIGNALS STORED IN SAID FIRST AUXILIARY REGISTER WILL PROVIDE THE RESULTANT NUMBER OR NUMBERS; CONTROL SIGNAL GENERATING CIRCUITRY TO PROVIDE INPUT SIGNALS TO SAID FIRST MULTIPLE OPERAND STORAGE REGISTER SUCH THAT EACH STAGE OF SAID FIRST OPERAND STORAGE REGISTER IS SET TO STORE A "1" SIGNAL; A PLURALITY OF SECOND ARITHMETIC CIRCUITS WHICH PERFORM AN EXCLUSIVE-OR LOGICAL CONNECTIVE FUNCTION ON CORRESPONDING STAGES OF SAID INVERTED BIT-DIFFERENCE SIGNALS AND SAID BORROW SIGNAL PATTERN PRODUCED BY SAID DIGIT-BORROW PROPAGATION CIRCUITS TO PROVIDE A FINAL GROUPING OF OUTPUT SIGNALS REPRESENTING THE COMPLEMENT OF THE DESIRED RESULTANT OPERAND; GATE CONTROL CIRCUITRY COUPLED TO THE OUTPUT STAGES OF SAID PLURALITY OF SECOND ARITHMETIC CIRCUITS TO PROVIDE SYNCHRONIZATION OF THE APPLICATION OF THE SIGNAL GROUPING REPRESENTING THE COMPLEMENT OF THE DESIRED OPERAND AS SIGNALS TO SWITCH CORRESPONDING STAGES OF SAID FIRST MULTIPLE OPERAND STORAGE REGISTER TO STORE A "0" SIGNAL WHEN A "1" SIGNAL IS PROVIDED AS AN INPUT FROM ONE OF SAID SECOND ARITHMETIC CIRCUITS, AND LEAVE UNALTERED THE PRESET "1" SIGNAL IN CORRESPONDING STAGES OF SAID FIRST MULTIPLE OPERAND STORAGE REGISTER WHERE A "0" SIGNAL IS APPLIED FROM ONE OF SAID SECOND ARITHMETIC CIRCUITS, THEREBY STORING THE RESULTANT OPERAND IN SAID FIRST OPERAND STORAGE REGISTER AT THE END OF THE ARITHMETIC OPERATION.