Generator of parity check bits

Claim 1

APPARATUS FOR GENERATING A SET OF PARITY CHECK BITS FOR A BLOCK OF SEQUENTIAL BINARY DATA BITS COMPRISING: A SOURCE OF BLOCKS OF SEQUENTIAL BINARY DATA BITS; A SOURCE OF CLOCK PULSES SYNCHRONOUSLY RELATED TO THE DATA BITS OF EACH OF SAID BLOCKS; AN OUTPUT TERMINAL COUPLED TO SAID SOURCE OF DATA BITS; A BINARY DIVIDER INCLUDING A PLURALITY OF INDIVIDUAL STAGES CONNECTED IN SERIES WITH RESPECT TO EACH OTHER; MEANS COUPLING THE OUTPUT OF SAID SOURCE OF CLOCK PULSES TO ONLY THE INPUT OF THE FIRST OF SAID SERIES CONNECTED STAGES OF SAID BINARY DIVIDER; A PLURALITY OF BINARY COUNTERS, ONE OF SAID COUNTERS BEING DIRECTLY CONNECTED TO SAID SOURCE OF DATA BITS TO RECEIVE ALL OF SAID DATA BITS; A PLURALITY OF GATE CIRCUITS, EACH OF SAID GATE CIRCUITS HAVING AN OUTPUT COUPLED TO A DIFFERENT ONE OF THE OTHERS OF SAID COUNTERS, A FIRST INPUT CONNECTED TO SAID SOURCE OF DATA BITS, AND A SECOND INPUT CONNECTED TO THE OUTPUT OF A DIFFERENT ONE OF SAID STAGES OF SAID BINARY DIVIDER TO CONTROL THE OPEN PERIODS OF SAID GATE CIRCUITS TO PERMIT EACH OF SAID OTHERS OF SAID COUNTERS TO RECEIVE THE BITS OF DIFFERENT GROUPS OF SAID DATA BITS, SAID GROUPS RECEIVED BY EACH OF SAID OTHERS OF SAID COUNTERS BEING SPACED APART BY INTERVALS OF EQUAL DURATION TO SAID RECEIVED GROUPS, THE NUMBER OF BITS IN SAID GROUPS INCREASING FROM COUNTER TO COUNTER BY THE POWERS OF TWO STARTING AT 2*; AND SWITCH MEANS COUPLED TO ALL OF SAID COUNTERS FOR SUCCESSIVE INTERROGATION OF THE CONDITIONS OF SAID COUNTERS AT THE CONCLUSION OF A DATA BLOCK AND PROVIDE A SET OF CHECK BITS FOR SAID DATA BLOCK, THE NUMBER OF CHECK BITS OF SAID SET OF CHECK BITS DETERMINING THE NUMBER OF DETECTABLE ERRORS.