Magnetic core transistor logic circuit

Claim 1

A LOGIC CIRCUIT COMPRISING A MAGNETIZABLE ELEMENT HAVING FIRST AND SECOND STABLE REMANENT STATES, SET AND RESET MEANS HAVING OUTPUT VOLTAGES SUFFICIENT TO DRIVE THE ELEMENT TOWARD THE FIRST AND SECOND STABLE STATES RESPECTIVELY, THE MAGNITUDE OF THE SET VOLTAGE BEING LESS THAN THAT OF THE RESET VOLTAGE, SAID SET MEANS NORMALLY CONNECTED TO SAID ELEMENT TO DRIVE THE ELEMENT TO THE FIRST STABLE STATE, SWITCHING AND TIMING MEANS INCLUDING A SWITCH, A GATE AND A SOURCE OF TIMING PULSE, THE SWITCH CONNECTED TO THE RESET MEANS AND TO THE SOURCE OF TIMING PULSES THROUGH THE GATE, THE TIMING PULSE OPERATING THE SWITCH ALTERNATELY TO RENDER THE RESET MEANS CONDUCTIVE AND NONCONDUCTIVE, THE ELEMENT BEING PARTIALLY RESET TOWARD THE SECOND STABLE STATE BY THE RESET MEANS WHEN CONDUCTIVE AND WHEN THE RESET MEANS IS NONCONDUCTIVE THE ELEMENT BEING SET FULLY OF THE FIRST STABLE BY THE SET MEANS, AND AN INPUT CIRCUIT RESPONSIVE TO PRESELECTED SIGNALS TO TURN OFF THE GATE AND DISCONNECT THE TIMING SOURCE FROM THE SWITCH WHEREBY THE RESET MEANS IS CONNECTED TO THE ELEMENT TO DRIVE THE ELEMENT FULLY TOWARD THE SECOND STABLE STATE.