US3231753A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Core memory drive circuit
Assignee: Unisys Corp
•
Filing: 1960-09-26
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Granted: 1966-01-25
•
Expires: 1980-09-26
Abstract
No abstract record available.
Inventors
- 👤 Jr Joseph Reese Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:30
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/661; H03K17/662; H03K17/663
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
141 words
A MAGNETIC CORE MATRIX SWITCH COMPRISING A CONSTANT CURRENT PULSE SOURCE, A TWO-TERMINAL LOAD, A BRIDGE CIRCUIT INCLUDING A SWITCH IN EACH ARM OF THE BRIDGE, THE CONSTANT CURRENT SOURCE BEING CONNECTED ACROSS ONE DIAGONAL OF THE BRIDGE AND THE TWO-TERMINAL LOAD BEING CONNECTED ACROSS THE OTHER DIAGONAL OF THE BRIDGE, EACH SWITCH INCLUDING A TRANSISTOR HAVING COLLECTOR, EMITTER AND BASE TERMINALSA, TWO OF THE TRANSISTORS BEING OPPOSITE CONDUCTIVE TYPE FROM THE OTHER TWO TRANSISTORS, A FIRST TRANSISTOR HAVING THE EMITTER AND COLLECTOR TERMINALS CONNECTED BETWEEN THE FIRST TERMINAL OF THE LOAD AND ONE TERMINAL OF THE SOURCE, A SECOND TRANSISTOR HAVING THE EMITTER AND COLLECTOR TERMINALS CONNECTED BETWEEN THE FIRST TERMINAL OF THE LOAD AND THE OTHER TERMINAL OF THE SOURCE, A THIRD TRANSISTOR HAVING THE EMITTER AND COLLECTOR TERMINALS CONNECTED BETWEEN THE SECOND TERMINAL OF THE LOAD AND SAID
Claim 2
Dependent Claim
141 words
A MAGNETIC CORE MATRIX SWITCH COMPRISING A CONSTANT CURRENT PULSE SOURCE, A TWO-TERMINAL LOAD, A BRIDGE CIRCUIT INCLUDING A SWITCH IN EACH ARM OF THE BRIDGE, THE CONSTANT CURRENT SOURCE BEING CONNECTED ACROSS ONE DIAGONAL OF THE BRIDGE AND THE TWO-TERMINAL LOAD BEING CONNECTED ACROSS THE OTHER DIAGONAL OF THE BRIDGE, EACH SWITCH INCLUDING A TRANSISTOR HAVING COLLECTOR, EMITTER AND BASE TERMINALSA, TWO OF THE TRANSISTORS BEING OPPOSITE CONDUCTIVE TYPE FROM THE OTHER TWO TRANSISTORS, A FIRST TRANSISTOR HAVING THE EMITTER AND COLLECTOR TERMINALS CONNECTED BETWEEN THE FIRST TERMINAL OF THE LOAD AND ONE TERMINAL OF THE SOURCE, A SECOND TRANSISTOR HAVING THE EMITTER AND COLLECTOR TERMINALS CONNECTED BETWEEN THE FIRST TERMINAL OF THE LOAD AND THE OTHER TERMINAL OF THE SOURCE, A THIRD TRANSISTOR HAVING THE EMITTER AND COLLECTOR TERMINALS CONNECTED BETWEEN THE SECOND TERMINAL OF THE LOAD AND SAID
References Cited (Backward Citations)
US3054067A
Cited
US2821639A
Cited
US3027546A
Cited
US2914748A
Cited
US2885574A
Cited
US2932007A
Cited
US3078379A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1969-01-24 | 1969-07-26 | 1970-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1973-01-24 | 1973-07-26 | 1974-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1977-01-24 | 1977-07-26 | 1978-01-25 | $7700.00 | Window Closed / Lapsed |