Sequential switching circuit which employs the turn-off delay of a saturated transistor for interim storage

Claim 1

THE COMBINATION COMPRISING: A PLURALITY OF BISTABLE STAGES CONNECTED IN CASCADE, EACH OF SAID STAGES INCLUDING A TRANSISTOR HAVING A BASE, AN EMITTER AND A COLLECTOR, A NEGATIVE RESISTANCE DIODE CONNECTED BETWEEN SAID BASE AND SAID EMITTER, MEANS CONNECTED TO SAID DIODE FOR BIASING SAID DIODE BISTABLY AND FOR BIASING SAID TRANSISTOR INTO SATURATION WHEN SAID DIODE IS BIASED IN A FIRST OF ITS TWO STABLE STATES, SAID TRANSISTOR HAVING A TURN-OFF TIME INCLUDING A SATURATION DELAY TIME AND A FALL TIME WHEN SAID DIODE IS SWITCHED FROM THE FIRST STABLE STATE TO THE SECOND STABLE STATE; A PLURALITY OF CAPACITORS EACH BEING CONNECTED BETWEEN THE COLLECTOR OF A DIFFERENT SAID TRANSISTOR AND THE BASE OF THE TRANSISTOR IN THE NEXT SUCCEEDING STAGE; A SOURCE OF SIGNALS EACH HAVING AN AMPLITUDE AND A POLARITY TO SWITCH EACH OF THE DIODES FROM THE FIRST STABLE STATE TO THE SECOND STABLE STATE AND A DURATION WHICH IS SHORTER THAN THE TURN-OFF TIME OF EACH TRANSISTOR; AND MEANS FOR COUPLING SAID SOURCE TO THE BASE OF EACH SAID TRANSISTOR.