Multi-level adder arrangement

Claim 1

AN ADDER FOR ADDING A BINARY NUMBER A=AN AN-1, . . . A2, A1 AND A BINARY NUMBER B=BN, BN-1 . . . B2, B1 INCLUDING A PLURALITTY OF ADD-ONE CIRCUITS, EACH ADDONE CIRCUIT INCLUDING AN ARRAY HAVING INPUT LINES TO WHICH SIGNALS ARE APPLIED REPRESENTATIVE OF A FIRST BINARY NUMBER AND A SECOND BINARY NUMBER, THE ARRAY INCLUDING OUTPUT LINES ON WHICH SIGNALS ARE SUPPLIED REPRESENTATIVE OF THE SUM OF THE FIRST AND SECOND NUMBERS, INHIBITORS DISPOSED AT SELECTED CROSSOVER POINTS OF THE INPUT LINES AND THE OUTPUT LINES WHEREBY SIGNALS ON THE INPUT LINES OPERATE THE INHIBITORS AND CONTROL THE SIGNALS ON THE OUTPUT LINES TO REPRESENT THE SUM OF THE FIRST AND SECOND NUMBERS, SAID PLURALITY OF ADD-ONE CIRCUITS BEING INTERCONNECTED TO FORM A MINIMUM NUMBER OF LEVELS L DEFINED BY THE EQUATION L=-(-LOG2 N)+1 WHEN N EQUALS THE TOTAL NUMBER OF PLACES OF THE LARGEST OF THE TWO NUMBERS A AND B, A PLURALITY OF OUTPUT LINES CONNECTED TO SELECTED ADD-ONE CIRCUITS IN THE VARIOUS LEVELS, WHEREBY THE ADDER RESPONDS TO THE SIGNAL REPRESENTATIVE OF THE NUMBERS A AND B AND GENERATES SIGNALS ON THE OUTPUT LINES REPRESENTATIVE OF THE SUM OF A AND B.