Digital computing systems

Claim 1

A CIRCUIT FOR CONTROLLABLY TIME SHIFTING INPUT PULSES REPRESENTING DECIMAL VALUES IN THE TIME DOMAIN IN RESPONSE TO INPUT DECIMAL VALUES AND COMPRISING: FOUR BISTABLE ELEMENTS, EACH COUPLED TO RESPOND TO A DIFFERENT ONE OF THE INPUT DECIMAL VALUES IN A 1, 2, 3, 3'' CODE, AT LEAST EIGHT GATING CIRCUITS, FOUR INDIVIDUAL DELAY CIRCUITS, EACH OF THE DELAY CIRCUITS BEING ASSOCIATED WITH A DIFFERENT ONE OF THE BISTABLE ELEMENTS AND EACH HAVING A CORRESPONDING ONE, TWO OR THREE-VALUED TIME DELAY INCREMENT, MEANS INTERCONNECTING THE SUCCESSIVE DELAY CIRCUITS IN AN ALTERNATING SERIES RELATIONSHIP WITH A FIRST GROUP OF FOUR OF THE EIGHT GATING CIRCUITS, SAID FIRST GROUP OF FOUR GATING CIRCUITS EACH BEING CONDITIONED BY A SELECTED STATE OF A DIFFERENT ONE OF THE BISTABLE ELEMENTS, SAID MEANS INTERCONNECTING A SECOND GROUP OF FOUR OF THE GATING ELEMENTS TO THE DIFFERENT DELAY CIRCUITS, EACH ONE OF THE SECOND GROUP OF GATING CIRCUIT BEING COUPLED TO BE CONTROLLED BY THE ALTERNATE STATE OF A DIFFERENT ONE OF THE BISTABLE ELEMENTS, AND EACH BEING COUPLED TO PROVIDE A BYPASS AROUND THE ASSOCIATED DELAY CIRCUIT TO THE NEXT SUCCEEDING DELAY CIRCUIT.