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US3215952A Expired / Lapsed US ⏱️ 0.0 years remaining

Transistor inverter with frequency stability provided by reverse base current injection

Assignee: AT&T Inc
•
Filing: 1963-03-05
•
Granted: 1965-11-02
•
Expires: 1983-03-05
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Abstract

No abstract record available.

Inventors

  • 👤 Richard P Massey

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 15:18
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/338; H02M3/3385; H02M3/3387; H02M3/3382; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5383; H02M7/53832; H02M7/53835

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 183 words
A FREQUENCY-STABILIZED INVERTER WHICH COMPRISES A SOURCE OF DIRECT INPUT CURRENT, A PAIR OF TRANSISTORS EACH HAVING AN EMITTER ELECTRODE, A COLLECTOR ELECTRODE, AND A BASE ELECTRODE, MEANS CONNECTING BOTH OF SAID TRANSISTORS TO RECEIVE CURRENT IN THEIR EMITTER-COLLECTOR PATHS FROM SAID SOURCE, AN OUTPUT TRANSFORMER CONNECTED TO RECEIVE EMITTER-COLLECTOR CURRENT IN ONE DIRECTION FROM ONE OF SAID TRANSISTORS AND IN THE OPPOSITE DIRECTION FROM THE OTHER OF SAID TRANSISTORS, FEEDBACK PATHS CONNECTED FROM SAID OUTPUT TRANSFORMER TO THE BASE AND EMITTER ELECTRODES OF BOTH OF SAID TRANSISTORS TO RENDER THEIR EMITTER-COLLECTOR PATHS ALTERNATELY CONDUCTING AND SUBSTANTIALLY NON-CONDUCTING IN PHASE OPPOSITION TO ONE ANOTHER, CAPACITIVE TIMING MEANS CONNECTED IN SAID FEEDBACK PATHS TO PROVIDE PRIMARY CONTROL OF THE RATE AT WHICH THE EMITTERCOLLECTOR PATHS OF SAID TRANSISTORS ALTERNATE CONDUCTIVITY STATES, AND MEANS TO INJECT INTO THE BASE ELECTRODE OF EACH OF SAID TRANSISTORS DURING SUBSTANTIALLY ALL OF EACH INTERVAL ITS EMITTER-COLLECTOR PATH IS CONDUCTING A REVERSE CURRENT AT LEAST AS LARGE AS THE MAXIMUM ICO FOR THAT TRANSISTOR, WHERE ICO IS THE TRANSISTOR COLLECTOR CURRENT WHICH FLOWS IN THE ABSENCE OF EMITTER CURRENT.
Claim 2
Dependent Claim 183 words
A FREQUENCY-STABILIZED INVERTER WHICH COMPRISES A SOURCE OF DIRECT INPUT CURRENT, A PAIR OF TRANSISTORS EACH HAVING AN EMITTER ELECTRODE, A COLLECTOR ELECTRODE, AND A BASE ELECTRODE, MEANS CONNECTING BOTH OF SAID TRANSISTORS TO RECEIVE CURRENT IN THEIR EMITTER-COLLECTOR PATHS FROM SAID SOURCE, AN OUTPUT TRANSFORMER CONNECTED TO RECEIVE EMITTER-COLLECTOR CURRENT IN ONE DIRECTION FROM ONE OF SAID TRANSISTORS AND IN THE OPPOSITE DIRECTION FROM THE OTHER OF SAID TRANSISTORS, FEEDBACK PATHS CONNECTED FROM SAID OUTPUT TRANSFORMER TO THE BASE AND EMITTER ELECTRODES OF BOTH OF SAID TRANSISTORS TO RENDER THEIR EMITTER-COLLECTOR PATHS ALTERNATELY CONDUCTING AND SUBSTANTIALLY NON-CONDUCTING IN PHASE OPPOSITION TO ONE ANOTHER, CAPACITIVE TIMING MEANS CONNECTED IN SAID FEEDBACK PATHS TO PROVIDE PRIMARY CONTROL OF THE RATE AT WHICH THE EMITTERCOLLECTOR PATHS OF SAID TRANSISTORS ALTERNATE CONDUCTIVITY STATES, AND MEANS TO INJECT INTO THE BASE ELECTRODE OF EACH OF SAID TRANSISTORS DURING SUBSTANTIALLY ALL OF EACH INTERVAL ITS EMITTER-COLLECTOR PATH IS CONDUCTING A REVERSE CURRENT AT LEAST AS LARGE AS THE MAXIMUM ICO FOR THAT TRANSISTOR, WHERE ICO IS THE TRANSISTOR COLLECTOR CURRENT WHICH FLOWS IN THE ABSENCE OF EMITTER CURRENT.

References Cited (Backward Citations)

US2993127A Cited
US3008068A Cited
US3034073A Cited
US3146406A Cited
US3134948A Cited
US3067378A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1968-11-01 1969-05-03 1969-11-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1972-11-01 1973-05-03 1973-11-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1976-11-01 1977-05-03 1977-11-02 $7700.00 Window Closed / Lapsed

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