Semiconductor time delay circuits

Claim 1

IN COMBINATION, A UNIJUNCTION TRANSISTOR HAVING AN EMITTER ELECTRODE AND A PAIR OF BASE ELECTRODES, SAID BASE ELECTRODES BEING ADAPTED FOR CONNECTION ACROSS A SOURCE OF ELECTRIC POTENTIAL, A TIMEING CIRCUIT INCLIDING IN SERIES A SUBSTANTIALLY LINEAR POTENTIOMETER AND A CAPACITOR TO BE CONNECTED ACROSS THE SOURCE OF POTENTIAL SO THAT THE CAPACITOR IS CHARGED THROUGH AN ADJUSTABLE PORTION OF THE POTENTIOMETER FROM THE SOURCE, SAID CAPACITOR BEING CONNECTED ACROSS THE EMITTER ELECTRODE AND ONE OF SAID BASE ELECTRODES TO APPLY A POTENTIAL TO SAID EMITTER ELECTRODE, SAID CAPACITOR DISCHARGING THROUGH SAID EMITTER ELECTRODE ANDSAID ONE BASE ELECTRODE WHEN THE CAPACITOR IS CHARGED TO THE PEAK POTENTIAL OF SAID EMITTER ELECTRODE AT WHICH THE TRANSISTOR FIRES, A LOAD DEVICE RESPONSIVE TO THE DISCHARGE CURRENT OF SAID CAPACITOR, AND FIXED RESISTOR MEANS IN SERIES WITH SAID POTENTIOMETER AND HAVING A VALUE EQUAL TO THE PRODUCT OF THE SLOPE OF THE POTENTIOMETER IN OHMS PER UNIT OF TIME AND THE DIFFERENTIAL OF THE ELECTRICAL ZERO OF THE POTENTIOMETER IN TIME UNITS AND THE PICK UP TIME OF SAID LOAD DEVICE.