Transistor time delay circuits

Claim 1

A TIME DELAY CIRCUIT WHICH COMPRISES (A) AN INPUT CIRCUIT FOR RECEIVING AN INPUT SIGNAL CHANGING BETWEEN FIRST AND SECOND LEVELS, (B) SAID INPUT CIRCUIT INCLUDING A TIME DELAY CIRCUIT HAVING A SERIES RESISTANCE AND SHUNT CAPACITANCE. (C) A RESET DIODE CONNECTED IN SHUNT WITH THE SERIES RESISTANCE AND POLED TO BRING THE VOLTAGE ON SAID CAPACITANCE SUBSTANTIALLY TO THE FIRST LEVEL OF THE INPUT SIGNAL UPON THE OCCURRENCE THEREOF, (D) THE CAPACITANCE DISCHARGING THROUGH THE SERIES RESISTANCE TOWARD THE SECOND LEVEL OF THE INPUT SIGNAL UPON THE OCCURRENCE THEREOF, (E) A TRANSISTOR SWITCHING CIRCUIT HAVING INPUT AND OUTPUT CIRCUITS. (F) MEANS FOR ESTABLISHING A THRESHOLD SWITCHING LEVEL OF THE TRANSISTOR INPUT CIRCUIT AT SUBSTANTIALLY THE SECOND LEVEL OF THE POINT SIGNAL UPON THE OCCURRENCE THEREOF, (G) A RESISTANCE AND DIODE CONNECTED IN SERIES BETWEEN THE SHUNT CAPACITANCE AND THE TRANSISTOR INPUT CIRCUIT IN THE ORDER NAMED, (H) SAID DIODE BEING POLED TO BE INITIALLY SUBSTANTIALLY NON-CONDUCTIVE WHEN THE INPUT SIGNAL CHANGES TO SAID SECOND LEVEL AND THEREBY SUBSTANTIALLY ISOLATE THE TIME DELAY AND TRANSISTOR INPUT CIRCUITS, (I) A SECOND CAPACITANCE SMALL COMPARED TO SAID SHUNT CAPACITANCE AND CONNECTED TO THE JUNCTION OF THE LAST-MENTIONED RESISTANCE AND DIODE, (J) AND MEANS FOR APPLYING REPETITIVE PULSES TO THE SECOND CAPACITOR HAVING AN AMPLITUDE LESS THAN THE DIFFERENCE BETWEEN THE INPUT SIGNAL LEVELS TO PERIODICALLY ADD PULSE VOLTAGES TO THE SHUNT CAPACITANCE VOLTAGE AT SAID JUNCTION, (K) THE PERIOF OF THE PULSES BEING PREDETERMINED TO YIELD ADDED VOLTAGES PASSING ABOVE SAID THRESHOLD SWITCHING LEVEL DURING THE DISCHARGE OF THE SHUNT CAPACITANCE SUFFICIENTLY TO SWITCH THE TRANSISTOR SWITCH CIRCUIT TO THE OPPOSITE STATE THEREOF AND BEING SHORT COMPARED TO THE TIME DELLAY BETWEEN THE CHANGE OF THE INPUT SIGNAL TO THE SECOND LEVEL AND THE SWITCHING.