Decimal adder-accumulator

Claim 1

A MAGNETIC CORE CIRCUIT COMPRISING FIRST AND SECOND MAGNETIC CORE COUNTER STAGES, THE MAGNETIC CORES OF SAID STAGES HAVING A SUBSTANTIALLY RECTANGULAR HYSTERESIS LOOP, A TRANSFER CIRCUIT INCLUDING COUPLING MEANS FROM SAID FIRST COUNTER STAGE TO A CAPACITOR STORAGE MEANS, MEANS ASSOCIATED WITH SAID FIRST COUNTER STAGES FOR GENERATING A NARROW VOLTAGE PULSE IN SAID TRANSFER CIRCUIT, CONNECTING MEANS FROM SAID CAPACITOR STORAGE MEANS TO SAID SECOND COUNTER STAGE INCLUDING A DELAY GATING SEMICONDUCTOR DEVICE, CONTROL MEANS FOR MAINTAINING SAID DELAY GATING SEMICONDUCTOR DEVICE-NON-CONDUCTING FOR BLOCKING THE INPUT PATH TO SAID SECOND COUNTER STAGE FOR A PREDETERMINED TIME THEREBY PERMITTING SAID CAPACITOR TO CHARGE UNDER CONTROL OF SAID VOLTAGE PULSE AND TO SUBSEQUENTLY DISCHARGE WHEN SAID GATING SEMICONDUCTOR DEVICE CONDUCTS TO PERMIT AN INPUT INTO SAID SECOND COUNTER STAGE WHEN SAID PATH IS UNBLOCKED OR, ALTERNATIVELY, WITHOUT DELAYING SAID VOLTAGE PULSE IN SAID CAPACITOR, TO UNBLOCK SAID GATING SEMICONDUCTOR DEIVCE TO PERMIT AN INPUT DIRECTLY INTO SAID SECOND COUNTER STAGE FROM SAID FIRST COUNTER STAGE OVER SAID TRANSFER CIRCUIT.